CDNS 3Q25 CC: "strong demand for its advanced EDA tools"
Cadence emphasized its leadership in enabling angstrom-era chip design, highlighting deep partnerships with TSMC and Samsung and strong demand for its advanced EDA tools.
During the Q3 2025 earnings call, CEO Anirudh Devgan spotlighted Cadence’s role in supporting angstrom-class semiconductor design, particularly in collaboration with leading foundries like TSMC and Samsung. He noted that Cadence’s tools are being used for 2nm and below nodes, which are part of the angstrom regime, and that the company is actively engaged in early enablement for these advanced processes.
Here are the key takeaways from the call regarding angstrom chips:
Strategic Positioning in Angstrom Design
- Cadence’s EDA platforms are being used for 2nm and sub-2nm nodes, which fall into the angstrom-class category.
- Devgan described this as a “multi-year wave of complexity,” requiring deep co-optimization across design and manufacturing.
- The company is investing in AI-driven design automation to handle the increased intricacy of angstrom-scale architectures.
Foundry Collaboration
- Cadence reaffirmed its close partnerships with TSMC and Samsung, both of which are pushing forward with angstrom-class nodes.
- These collaborations include early access programs, where Cadence tools are validated and tuned for next-gen process technologies.
Market Demand and Backlog
- The angstrom transition is contributing to a surge in design activity, especially in AI, hyperscale infrastructure, and advanced packaging.
- Cadence reported a backlog exceeding $7 billion, with strong bookings tied to customers preparing for angstrom-era chips.
Technical Enablement
- Devgan emphasized that angstrom design isn’t just about smaller transistors—it involves new materials, 3D integration, and system-level co-design.
- Cadence’s Virtuoso and Innovus platforms are being enhanced to support these needs, including multi-physics simulation and chip-package co-optimization.
If you’re tracking angstrom-class enablement across the EDA stack or want to compare Cadence’s positioning to Synopsys or Siemens EDA, I can pull those details too. Want to dive deeper into their roadmap or customer adoption patterns? |
