| | | TSMC’s 2nm race heats up
by Nick Farrell on03 November 2025
Qualcomm and MediaTek join Apple at the front line
The semiconductor arms race has entered another round, with TSMC speeding ahead on its 2nm roadmap.
According to the Commercial Times after the Fruity Cargo Cult Apple secured first dibs on the upcoming N2 process, Qualcomm and MediaTek have now jumped aboard, accelerating their own adoption plans and pushing the enhanced N2P version forward.
Their combined demand has forced TSMC to move up its A16 process schedule, which is now expected to begin trial production as early as March next year.
According to sources in the supply chain, this marks a new chapter in what TSMC calls “Moore’s Law 2.0”. The company is leading the industry’s shift into the Gate-All-Around Field Effect Transistor era, where transistors are vertically stacked for better performance and efficiency.
Job's Mob is expected to debut the technology in its A20 chip for the iPhone 18, pairing it with advanced WMCM packaging. Qualcomm and MediaTek will follow with N2P-based designs targeting the next generation of AI-capable flagship smartphones.
Costs, however, are spiralling. With wafer complexity and memory prices both on the rise, analysts warn that flagship chip prices will climb sharply.
MediaTek has already said it will “adjust pricing and capacity strategically” to preserve margins. TSMC’s 2nm capacity is expected to remain scarce, with production estimated at 15,000–20,000 wafers per month by the end of this year and more than doubling by late next year. The bulk of that will go to Apple, Qualcomm, MediaTek and high-performance computing customers.
Yield rates for 2nm are improving fast. TSMC’s roadmap shows N2P and A16 ramping into full mass production in the second half of next year, although progress on N2P has been quietly accelerated to meet Qualcomm and MediaTek’s launch schedules. MediaTek has confirmed its first N2P chipset will arrive in late 2026, targeting premium AI phones and flagship devices.
The A16 process represents the next step in TSMC’s evolution, featuring a new and unfortunately named backside power delivery network (BSPDN) that shortens current paths and boosts energy efficiency. Nvidia is expected to be among the first to adopt the A16 node for its next-generation AI GPUs, which demand extreme power density and thermal management.
With wafer prices reportedly topping $30,000 each, the A16 process will be reserved for only the biggest spenders in AI and HPC design.
TSMC’s deputy co-chief operating officer, Hou Yongqing said: "Moore’s Law 2.0 isn’t about shrinking transistors anymore, but about “creating greater value through software, hardware and system integration.”
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