Well, I'm not Paul, but every indication is that it is entirely possible to put a 100 MHz external bus on a socket 7 processor, and some people are overclocking existing parts to 83 MHz now. Reportedly, AMD was going to offer a 100MHz version of the K-6/K-7 to be used with a 100 MHz Via chip set that is due out later this year.
Slot 2 will use memory running at full CPU speed, which will be VERY expensive, and the processor will have to run at a multiple of the clock speed, which will be 100 MHz, so it won't be a 233, it would have to be a 200, 250, 300 or 350. (the clock to CPU ratios so far have been at multiples of 0.5).
Also, the PII 233, 266 and 300 are 0.35 micron devices, the 333 and all faster are (will be) 0.25 micron.
The bottom line of this is that probably the slowest chip that would run as you suggest would be a 333 overclocked to 350 (350 will be the lowest speed that Intel will offer with a 100 MHz bus).
However, both slot 1 and slot 2 are less sensitive to the PCI bus speed than socket 7 devices are, because slot 1/2 devices have the cache closely coupled to the CPU (the "dual independent bus", running at half of the processor clock in slot 1, and at the processor clock in slot 2), while a socket 7 device accesses cache at the PCI bus speed. So, even for a slot 1 CPU vs. socket 7 CPU, you are talking about cache access speeds of 116 MHz vs. 33 MHz. Socket 7 is much slower, hence it benefits much more from the speedup of the clock.
Paul, do I have this mostly right ? |
