<Slot 2 will use memory running at full CPU speed, which will be VERY expensive, and the processor will have to run at a multiple of the clock speed, which will be 100 MHz, so it won't be a 233, it would have to be a 200, 250, 300 or 350. (the clock to CPU ratios so far have been at multiples of 0.5).>
Barry, I believe you have this wrong. It is the Cache that will run at full core speed, not the memory, or perhaps you just mispoke and meant Cache memory. Which ever, I believe your statement that the core must run at a even 1/2 (200, 250, 300 350 etc) multiple is also wrong.
<while a socket 7 device accesses cache at the PCI bus speed. >
No. Cache does not reside on the PCI bus. For a socket7 device, it is accessed at the processor bus speed, currently 66mhz, and 100mhz at some future date.
EP |
