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Technology Stocks : ASML Holding NV
ASML 1,046+3.0%9:52 AM EST

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From: BeenRetired12/16/2025 8:08:27 AM
1 Recommendation

Recommended By
Tobias Ekman

   of 42727
 
Copilot: 7nm Tesla Dojo speaks to NXTi quality.

Ah — got it. Switching from NXE (EUV) to NXT (193i DUV) changes the entire interpretation. And yes, Dojo being on TSMC N7 (DUV) absolutely speaks to the quality and maturity of the NXT:2XXXi family.

Let’s break it down cleanly.

What “NXT:2XXXi” Means

NXT:2XXXi refers to ASML’s 193nm immersion DUV scanners, the backbone of multi-patterning nodes like:
  • TSMC N7
  • TSMC N6
  • Samsung 7LPP (partial)
  • Intel 10nm (various variants)
These tools include models like:
  • NXT:1980i
  • NXT:2000i
  • NXT:2050i
  • NXT:2100i
They are the workhorses of high-volume DUV lithography.

So what does Dojo on N7 say about NXT:2XXXi quality?

1. NXT:2XXXi was mature enough to support massive multi-patterning at scale

TSMC N7 uses:
  • quadruple patterning for critical layers
  • triple patterning for others
  • 193i immersion for all FEOL layers
This only works if the NXT:2XXXi tools have:
  • extremely tight overlay
  • low CDU variation
  • stable focus control
  • high uptime
Dojo is a huge die with enormous SRAM arrays. If DUV overlay were unstable, yield would collapse.

So Dojo’s manufacturability implies:

NXT:2XXXi tools were extremely mature and stable for high-volume HPC production.

2. NXT:2XXXi had better yield predictability than early EUV

Even though EUV was available (NXE:3400B/C), Tesla chose N7 DUV.

Why?

Because NXT:2XXXi tools had:
  • higher uptime
  • lower defectivity
  • better mask lifetime
  • more predictable multi-patterning behavior
For a giant HPC tile, predictability beats density.

This indirectly says:

NXT:2XXXi quality exceeded early EUV tools for large-die economics.

3. NXT:2XXXi overlay performance was good enough for Dojo’s interconnect-heavy mesh

Dojo’s architecture depends on:
  • wide metal buses
  • dense routing
  • tight via alignment
  • consistent SRAM cell geometry
If DUV overlay drifted even slightly, the mesh would fail.

So Dojo’s success implies:

NXT:2XXXi overlay met HPC-grade tolerances across a very large die.

4. NXT:2XXXi throughput was high enough to make multi-patterning economical

N7 requires many DUV exposures per wafer.

If NXT:2XXXi throughput were poor, N7 would be too expensive for a chip like Dojo.

The fact that Tesla chose N7 means:

NXT:2XXXi throughput was high enough to keep cost per wafer acceptable.

Bottom Line

Yes — Dojo being built on TSMC N7 (DUV) is a strong endorsement of the NXT:2XXXi family.

It implies:
  1. NXT:2XXXi overlay and CDU were extremely mature.
  2. NXT:2XXXi defectivity was lower and more predictable than early EUV.
  3. NXT:2XXXi throughput made multi-patterning economical for huge dies.
  4. NXT:2XXXi stability enabled massive SRAM arrays and mesh interconnects.
In other words:

Dojo’s existence is proof that NXT:2XXXi was good enough to support one of the most demanding DUV-patterned chips ever built.

If you want, I can map:
  • NXT:1980i ? 2000i ? 2050i ? 2100i evolution
  • Which specific NXT tools TSMC used for N7
  • How NXT:2XXXi compares to SMEE’s SSA/SSB tools in China
Just tell me where you want to take it.

Why Dojo would avoid EUV

Dojo is an SRAM-heavy, interconnect-bound architecture. EUV doesn’t help much here:

SRAM doesn’t scale well with EUV

SRAM cell size barely shrinks from N7 ? N7+. Dojo’s tile has 1.25 MB SRAM per node and a massive mesh of nodes.

Interconnect dominates performance

Dojo’s mesh relies on:
  • thick metal layers
  • predictable routing
  • low-resistance wires
EUV doesn’t improve metal layers — it mostly helps with FEOL patterning, not the wiring that defines Dojo’s performance.

Yield matters more than density

Dojo tiles are large. EUV at the time (2019–2021 design window) had:
  • lower yield
  • higher cost
  • less maturity
Tesla needed a stable, high-yield HPC node.

Final Answer

Tesla Dojo’s 7nm chip is almost certainly fabricated on TSMC’s N7 (DUV-only) process, not the EUV-based N7+. The architecture (SRAM-heavy, interconnect-bound), the design timeline, and the manufacturing economics all point to no EUV usage.

If you want, I can map how this choice compares to:
  • Cerebras WSE-3 (TSMC 5nm EUV)
  • DensityAI’s wafer-scale strategy
  • Multibeam’s multi-column e-beam roadmap
Just say the word.
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