More on STM's .18 micron products and plans..............
A service of Semiconductor Business News, CMP Media Inc.
Story posted at 7:30 a.m. EST/4:30 a.m. PST, 3/4/98
SGS-Thomson starts 0.18-micron prototyping
CROLLES, France--In the second half of 1998, SGS-Thomson
Microelectronics and its partners here plan to begin producing prototypes of
ICs using a new 0.18-micron CMOS process technology, which is aimed at
offering system-on-chip designs for high-performance and low-power
applications.
The European chip maker this week announced the completion of the first
phase of development of the next-generation HCMOS-8 process, which
yields drawn gates of 0.18 micron and effective gate lengths of 0.15 micron.
Meanwhile, SGS-Thomson said it has also released for production a
0.25-micron (0.20-micron L-effective ) CMOS technology, known as
HCMOS-7. The process will be used in the Crolles fab to produce
'system-on-chip' products incorporating tens of millions of transistors
combined with embedded memory for telecom, digital consumer and PC
applications, according to SGS-Thomson. Volume production using this
process is expected to begin in 1998.
"We are among the first companies world-wide to reach these levels of
process development, which underlines the leading position we have on the
market today," said Joel Monnier, corporate vice president of central
research and development for SGS-Thomson. "Our researchers are now
working to develop the next generations. Semiconductors today are
extremely complex and to commercialize HCMOS-7 in one year is a great
achievement."
Working on process development with SGS-Thomson are France
Telecom's CNET in the "Centre Commun" in Crolles as well as Philips
Semiconductors. The SGS-Thomson team is also participating in the
pan-European MEDEA program as well as in the basic research carried out
by GRESSI, which is an advanced R&D consortium formed in Grenoble by
CEA LETI and France Telecom CNET. |
