Nice growth expectations for this product. "Lucent expects total sales of FPSCs to grow from nearly zero several years ago to $154 million by 2001."
Lucent to merge FPGA, standard-cell macros
By Anthony Cataldo
ALLENTOWN, PA. -- Downplaying the need to develop FPGAs with a million or more gates, Lucent Technologies has opted to leverage its new 0.25-micron process technology to create FPGAs combined with its standard-cell hard macros. The company announced in early March a new FPGA architecture that will take it down that path while also providing features to ease system-level integration. The first products will appear by the middle of this year.
Lucent claims it has developed the hardware needed to plug an FPGA region into a standard-cell design, and has honed its HDL-based design environment to allow designers to start the transition to the new hybrid parts, which it calls Field Programmable Standard Cell (FPSC) devices. Lucent's plans run counter to those of PLD leaders Altera Corp. and Xilinx Inc., both of which aim to push high-density, 0.25-micron devices from 1 million to 2 million gates with an emphasis on soft cores.
"We don't think it makes a whole lot of sense to do 1 million-gate designs," said Barry Britton, strategic-marketing manager for FPGAs at Lucent Technologies (Allentown, Pa.). "[Our decision] comes down to wanting to do more of the system-level things that customers would rather have done for them, such as new clocking features and microprocessor interfaces. And we're hoping to expand that to go to FPSCs. We've seen that most of the designs tend to be an improvement from a previous design, either by adding features or improving speed. One way to do that is to put part of the design you know works very well into standard cell and put the other in programmable logic."
Interface challenge
Such a device could prove to be useful to data-communication and telecommunication-equipment OEMs, which must grapple with fluctuating communication protocol standards. Lucent expects total sales of FPSCs to grow from nearly zero several years ago to $154 million by 2001.
One of the biggest challenges to building such a device is developing an interface layer between the different standard-cell and FPGA fields. "The interface is defined, so it's going to be robust and we're gong to be able to control that interface to do lots of things," Britton said, without elaborating.
The company said its Orca series 3 family represents the first step down the road to FPSCs. Two features in particular emphasize system-level integration: new clocking capabilities and microprocessor interfaces.
Each device has two phase-locked loops that enable clock multiplication and division, ranging from 1/8 to 64-times. Perhaps more important, the external bus speeds and the internal device clock can differ as much as 8x to allow the I/O to run more slowly than the chip or vice versa.
Orca series 3 also can directly interface to either multiplexed addressed Intel i960 or split-addressed PowerPC microprocessors. Britton said this feature should cover 95 percent of the system designs it will target. Other CPUs and digital signal processors will require external glue logic.
Additionally, Lucent doubled the number of logic blocks in each cell and improved performance of the programmable functional unit within each cell in several ways: by adding a new register dedicated to pipelining functions; doubling the number of look-up tables, from four to eight, strung together by dedicated data paths for improved routing; and quadrupling the density and tripling the throughput of dual-ported RAM.
One of the more exotic features is a CPLD-like supplemental logic and interconnect cell (SLIC) that sits next to each programmable functional unit. These cells are designed to handle functions for which look-up tables are ill-equipped, such as wide random logic, large state machines and decoders, Britton said.
Orca Foundry development software includes features such as a timing-optimized mapper, ASIC-like static timing engine, logical preference language and back-annotation engine for submicron design. "This is an environment for the ASIC designer," said Frederick Koons, FPGA software strategic-marketing manager for Lucent. "This is going to be the baseline architecture for future products."
The Orca series 3 family is available now in 80,000 and 116,000 system-gate densities. In lots of 25,000, prices run $63.20 and $87.60, respectively. The company will roll out versions ranging from 48,000 to 225,000 gates throughout the year. |
