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To: E. Graphs who wrote (10866)	3/15/1998 4:17:00 PM
From: shane forbes	Read Replies (1) of 25814

E: RE: ALTR 40+- AMD 20+- ADI 30+- IDTI 13+- IMG 10+- NSM 20+- AMAT 24+- ASMLF 50+- JBIL 39+- KLIC 23+- LSI 22+- LRCX 27+- LSCC 47+- MU 30+- ZITL 14+- XLNX 40+- TQNT 22+- Here's the way I'll just guess at what is comfortable and based on support levels (mostly from memory): RE: ALTR 38+- AMD 20+- ADI 28+- IDTI 13+- IMG ??+- NSM 20+- AMAT 28+- ASMLF ??+- JBIL ??+- KLIC 20+- LSI 21+- LRCX 27+- LSCC ??+- MU ??+- ZITL ??+- XLNX 40+- TQNT ??+- (the ?? means I don't have a clue because I don't follow. Also not immensely familiar with IDTI and XLNX but left as is.) I'll just add: VLSI: 20+- (but conern for new product introductions - not as good a pipeline as LSI I think, but like the "fabless" route they are taking.) COHU: 36+- UTR 17.5+- HELX 20+- CUBE 18+- ATML 15+- (what's going on here!) SVGI 20+- (but execution risk? or are they lying to all of us?) There also may be a concern about some of the analog guys since they supply the millions of chips types where SEA will affect them more than say an LSI. Shane.

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