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To: Pigboy who wrote (50797)3/19/1998 12:02:00 PM
From: Paul Engel  Read Replies (1) of 186894
 
Pigboy - Re: "AMD K6 ...Are they going to try to change this or is it virtually impossible to architect the chip to do so>?"

They are trying - but unsuccessfully. The K6 layout implements the metal routing upside down - they use the lowest level metal for power/ground bussing instead of interconnect for high speed signalling.

Also, AMD's process development is way behind Intel's. They cannot produce devices with enough drive to get their speeds up to levels comparable to Intel's. You might want to review many of the past posts by Yousef on this and the AMD threads. He has documented AMD's difficulties very well.

I won't even mention their yield problems!

Re : "How does this prevent them from getting multiple processors working? "

In theory, AMD could develop (or have independently developed) the glue logic to combine several K6's in an SMP configuration. But they don't have a full speed L2 cache like the Pentium Pro or upcoming Deschutes/Slot 2 - so the performance will be relatively poor - and "non-standard".

AMD is trying to add a back side cache to the K6 - their upcoming K6+3D - so they have admitted that Intel's Slot approach is the right way to go. Now they are playing catch-up. However, their die size will increase significantly, further reducing their already poor yields.

Re: " have you ever thought about writing something yourself
(ie. a book, novel)? "

I think about this from time to time. In a prior "life" I used to write technical articles and documents describing semiconductor technology and reliability - aimed at a non-technical/slightly technical audience. That was a lot of fun - most of the time!

Paul
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