More info on LSI Logic's .18 micron process.........
techweb.cmp.com
<<At the same time, device performance depends more on the
signal-propagation delay along the metal routes than the speed of the
transistors themselves because of the high reliance on interconnect in
deep-submicron technology. To help solve that problem, LSI worked with
one of its equipment suppliers to develop a low-K dielectric material,
which reduces the dielectric constant compared with conventional silicon
dioxide and therefore reduces signal delays caused by interconnect
resistance and capacitance. The metal scheme also provides for the top
two layers to be thicker and placed at a higher pitch (for lower resistivity)
and allows for the longer global routes to be placed high using hierarchical
place and route.
Vasishta made a point of explaining why LSI chose not to go with copper
interconnect, which is being shepherded into next-generation designs by
some companies, notably IBM Microelectronics. He said LSI would
consider using copper in the second generation of the 0.18-micron process
or in follow-on technologies
"There's a lot of talk about copper, but it's not as if we don't have the
ability," he said. "The issue is whether to include it now. It's not a mature
technology; the equipment is just not available. If we wanted that capability
we'd essentially have to upgrade the equipment sets, and that cost has to
be passed on to customers. Defect densities would also be higher." Even
without copper, LSI said the low-K dielectric and new metallization
schemes will help make it possible to integrate RF/IF functions in pure
CMOS, which could be particularly attractive to cellular phone designers
that want to combine the digital and analog front end on one chip. LSI
claims it can achieve greater than 70-GHz for the n-channel and more than
40-GHz for p-channel, and achieve more than 110-dB isolation, posing a
challenge to bipolar, gallium-arsenide and nascent silicon-germanium
technologies.
"Essentially, we can build an RF inductor in the top layer of the metal,"
Vasishta said. "One thing we did was introduce a spiral inductor. This gives
us tuning capabilities that are usually done off-chip. Now with our
proprietary schemes we can get the Q-factor high."
Aside from moving to a finer process technology, LSI made strides to
bolster transistor density by introducing a shallow-trench isolation scheme,
which makes transistors more planar and less susceptible to crosstalk. The
upshot is that the company can now pack 65,000 usable gates per square
millimeter, or 223 million transistors on a chip.
The G12 is also equipped with dual-gate oxide transistors that will allow
the device to drive external devices that operate at 3.3 V or 2.5 V, such as
high-speed DRAMs, as well as accommodate mixed-signal cores
optimized for 3.3 V.>> |
