I can tell you one thing: Cornell's statement about their etching (111) silicon not being directly relevant to the semiconductor industry is an understatement.
Logic chips are built on (100) substrates, which have the lowest number of atomic bonds along the exposed surface plane (where the active devices will be fabricated). (111)-oriented wafers have the highest number of bonds. At the surface, these bonds have nothing to attach themselves to, so are "dangling." Dangling bonds degrade performance, which is precisely why (100) orientation is used. Finding a way to make 'flat' (100) is great, but I can't even think of an application for flat (111) except to study interface properties. (Well, actually, a lot of MEMS are designed on non-(100) surfaces).
The (###) are Miller indices, and refer to the orientation of the silicon crystals. Etching is very orientation-specific, so whatever is developed for (111) will work quite differently on (100).
How does it affect IPEC? Not at all, IMHO, unless they don't understand the difference. :)
Steve |
