Why Celery is cacheless? - Cost of cache.
Current P-II 233-300 use 4 pieces of
167MHz CMOS 1Mbit Synchronous SRAM [æPD431632L]
As per NEC (old) news release
ic.nec.co.jp
"price of the new product is expected to be 2,000.=$15"
So, 4x15=$60 alone, maybe $40 today. At least.
Count on other parts of P-II brick:
1 IC: i82459 - probably TAG RAM and/or ECC;
1 Printed board, 12 layers at least;
92 SMT capacitors;
12 SMT resistors;
36 SMT resistor networks;
1 Aluminium thermal plate 130x50x4mm, precisely machined
in all six surfaces, plus some fine grooves;
2 spring holders, steel;
8 machined pins, steel;
4 parts of plastic cover with locks;
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So, Q: How much it may cost to assemble all this?
To order and supply parts? For quality control?
For "Deschutes"(?) P-II-333 and up, somewhat faster
synchronous cache must be used. If it would be again
from NEC, then it could be æPD464318L/36L or
æPD464518L/36L or alike. Again, in accord with
ic.nec.co.jp
"The price of the new products is 20,000 yen to 25,000
yen per unit," or $150+. Not too shabby. No wonder
Intel is going to manufacture this cache themselves,
222mm2 die size on 0.35um technology (as Pauleron
told us).
In any way, silicon area is silicon area, no matter
what you print over it. 130 + 222 seems to be smaller
than 68mm2 for Intel stalwarts. Sounds interesting.
BTW, Celery today: 3 vendors, 199-212 price range. |
