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Technology Stocks : IDTI - Dark Horse For '96 ?
IDTI 48.990.0%Mar 29 5:00 PM EST

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To: Jim Green who wrote (993)3/21/1996 12:47:00 AM
From: Marshall   of 1139
 
The full-text article as printed in EETimes is much more specific

as to what we all wanted to know, here is most of what wasn't in the
release:

SMALLER ARRAYS
There is a second major benefit to breaking the memory into a
cluster of smaller arrays, Sando said. Since not all the arrays, and
hence few of the sense amps, will be active on any one cycle, IDT can
dynamically power down most of the current sinks on the die most of
the time. That results in dramatic reductions in power consumption
compared with conventional DRAM.

The first use of the new technology will be in a cache memory chip,
which IDT expects to introduse in a couple of weeks. Sando said that
the part would be almost pin-compatible with the industry-standard
32k x 32 burst-synchronous SRAM used in Pentium Level II caches.
There will be a few additional signal pins, used to connect the new
memory devices to the system controller chip on a Pentium
motherboard. Otherwise, the parts will be drop-in replacements for
the burst-synchronous SRAMs, executing 3-1-1-1 reads at 66Mhz.
The only exception to the 3-1-1-1 timing is when a read or write
coincides with an internal refresh cycle.

"The parts require a core-logic chip set that is designed to work with
them," Sando explained. "When we announce the memory devices,
we will also announce that several existing core-logic designs already
support the parts. We expect other vendors to join in during 1996.

IDT is betting a lot on the new technology. The company will
proceed with the L2 cache chip announcement, even in the face of
collapsing prices for 32k x 32 burst-synchronous SRAMs. Further, the
company has aggressive plans to use Fusion Memory across much of
its product line this year. Sando explained that there were Fusion
Memory projects in the dual-port, FIFO, embedded control-and-
communications chip products groups at IDT. The new memory
arrays would be used to complement IDT's existing SRAM expertise in
areas where sub-10nS asynchronous access is not necessary.

The company is currently running Fusion Memory devices on its 6-
inch line in San Jose, Calif.
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