SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : AMD:News, Press Releases and Information Only!
AMD 213.43+6.2%Dec 19 9:30 AM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Elmer who wrote (5720)4/23/1998 11:27:00 AM
From: Ali Chen  Read Replies (1) of 6843
 
Elmer, <Processors don't have redundency (except possibly for the
L1 cache), so a defect that would kill a processor might be repairable on a SRAM. Of course if the rumors about Intel's yields are true, there aren't many bad die to recover.>

I believe you got it all backwards as usual.
The L1 dominates processor's die area, and the
probability that a defect hits the L1 area would
dominate. Intel yields are "good" BECAUSE of the
redundancy technique, not opposite as you tend
think. IMHO.

Ali
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext