Mr. Sam,
Caught this listening to the Cymer conference call and thought that you would be the person that would have the answer. Here is the relevant passage in a transcript of the call(Thanks to ScottMcI):
================================================================
Hays: Ok, thanks. Just a follow-up - I was interested in your comments with regard to bottlenecks to reduced line widths. Could you give us an idea perhaps of what some of those other issues that your chipmakers are facing are? In order to reduce line widths?
Akins: Well for example, let's stay to something relatively close to the photolithographic process, the new photoresist - the new high-sensitivity chemically-amplified photoresist - of course have to see stripping technologies, ashing technologies, as well as cleaning technologies, and etch technologies, which are compatible with those new resists. Also, the CMP process, which of course is essential to maintaining flatness for increasing the depth of focus or utilizing the relatively small depth of focus for lithography tools, is seeing its set of challenges as well.[Emphasis mine - C.S.] It's really a whole set or whole family of processes that need additional tuning over time. This is not unusual, and this process will never cease, as all chipmakers will be continuously improving those processes in an attempt to improve their yields and reduce costs.
Message 4196200
================================================================
Do you know what the CMP challenges referred to are, and, if so, do you know how well Speedfam is addressing these relative to their competitors. Also, does Applied Materials have any material advantage here due to their more intimate knowledge of the overall semiconductor manufacturing processes? Thanks...
Craig |
