More on NEC's sub-micron roadmap -- .18 and .15 micron available in October 1998.
techweb.cmp.com
<<NEC is offering two new CMOS process technologies (0.18-micron and
0.15-micron) that will support both mainstream and high-end designs. The
high-performance 0.15-micron (drawn) unified RISC process is targeted at
customers requiring high-end microprocessor and high-speed networking
and it is supported by third-party commercial libraries. The second family is
a low-power, mainstream 0.18-micron (drawn) unified CMOS process that
includes the building blocks for an extensive system IP portfolio well-suited
for a vast amount of applications for consumer electronics. >>
From a different press release:
NEC Electronics Unveils New ASIC Strategic Roadmap for Year 2000
Industry Analysts Again Name NEC #1 Worldwide ASIC Vendor as NEC Announces
0.18- and 0.15- Micron Process Technologies
SANTA CLARA, Calif., April 27 /PRNewswire/ -- With the unveiling of its advanced 0.15- and 0.18-micron ASIC process technologies, NEC Electronics Inc. also announced today that NEC Corporation has been named the world's number one ASIC supplier for the fifth consecutive year by industry analysts, IBS and Dataquest. This rating is the result of NEC's unique ability to fulfill the multimedia market's needs with high-performance ASIC products and a wide breadth of advanced cores. NEC Electronics also unveiled its new ASIC roadmap, which includes products based on 0.18-micron drawn (0.13 L-effective) and 0.15-micron drawn (0.1 L-effective) process technologies. This new roadmap, together with secured production capacity, is expected to help NEC maintain its ASIC leadership in both North America and around the world. With the addition of new ASIC cores, NEC plans to continue its major contributions to the further development of the system-on-a-chip (SOC) trend.
"NEC has been carefully studying market needs and we have invested much time and energy into building an infrastructure to make us a very competitive system-on-a-chip supplier," According to Dr. Hajime Sasaki, senior executive vice president of NEC Corporation. "Customers need the latest cores, interfaces and process technologies that are the essential building blocks for system-on-a-chip design. NEC's expertise in systems operation, along with its leading-edge technology and manufacturing capacity, continue to make us a preferred ASIC and system-on-a-chip supplier."
"Our assessment of the system-on-a-chip market in the year 2005 shows it to encompass approximately 50 percent of the total IC business," said Dr. Handel Jones, president, International Business Strategies. "We feel that within the high-volume application segments only two or three major vendors will be able to survive. To be in the system-on-a-chip business a company needs large financial, technical and applications resources. NEC has all of the key capabilities required to be one of the leaders in the system-on-a-chip market."
NEC's 0.18- and 0.15 Micron (Drawn) Process Technology
NEC is offering two new CMOS process technologies (0.18-micron and 0.15-micron) that will support both mainstream and high-end designs. The high-performance 0.15-micron (drawn) unified RISC (UR) process is targeted at customers requiring high-end microprocessor and high-speed networking and it is supported by third-party commercial libraries. The second family is a low-power, mainstream 0.18-micron (drawn) unified CMOS (UC) process that includes the building blocks for an extensive system IP portfolio well-suited for a vast amount of applications for consumer electronics.
Both architectures utilize a seven-layer metal process and support more than 34 million usable gates. While the first phase products will use both aluminum and copper, second phase devices will be based on copper only. Providing more than double the gate density, with 80,000 gates per square millimeter, the families will also offer one-and-a-half times the performance of previous ASIC technology with an on-chip frequency of approximately 500 megahertz (MHz). The 0.18 process technology also offers low power dissipation of 0.02 microwatts (uW) per megahertz per gate.
The new families will have a contacted metal pitch of 0.56-microns for layers one through five, and a pitch of approximately 1.12 micron for layers six and seven. Both approaches involve a low dielectric insulator to resolve performance degradation caused by fine pattern interconnects that are below 0.2 micron. The power supply for products developed with this advanced technology is 1.8 volts (V) for internal areas with options of 1.8V, 2.5V and 3.3V for I/O power supply.
High-Speed Interface Support
As systems continue to expand bus widths, while also integrating more functions onto a single chip, support for high integration is critical to the input/output (I/O) function. Products in these high-performance areas require fast I/O signal interfaces for both data and clock transmission. NEC offers extremely high-density I/O buffers at a 30-micron pad pitch, resulting in over 3000 I/O pads on a single chip.
The new NEC ASIC families will continue to support leading interface standards, including LVDS (low-voltage differential signaling), HSTL (high-speed transceiver logic), GTL+ (PentiumPro(R) version of gunning transceiver logic), PCI (peripheral component interconnect), AGP (accelerated graphics port), p-ECL (pseudo emitter-coupled logic), and SSTL (stub series transceiver logic).
According to Eikichi Wakamatsu, general manager of System ASIC Division at NEC Corporation, "This strategic ASIC approach has evolved into a very strong NEC ASIC infrastructure. Our broad range of system IP cores allows for all the necessary building blocks to be merged together into one piece of silicon. Having access to IP that works will help designers reduce time and cost and increase functionality."
New MIPS RISC, DRAM, RAC and Multimedia Cores
To support NEC's move toward system-on-a-chip solutions, several new ASIC cores have been added to the 0.25-micron libraries. The new cores will also be supported in the 0.18- and 0.15-micron families. In addition to NEC's current proprietary 32-bit RISC V850-based core offering, the company has added its high-performance, 64-bit MIPS RISC cores, which have been widely accepted in embedded markets, including game, printer and personal digital assistant (PDA) applications. The ASIC cores based on NEC's 0.25- and 0.18-micron process technology will include derivatives of the VR4100(TM), VR4300(TM) and VR5400(TM) families. These processor-based ASIC cores run at 133MHz to 200MHz. In order to help enable board designers to migrate towards system-on-a-chip technology, NEC will also make available the existing peripheral macros with stand-alone microprocessors.
Other Supported Cores
NEC's ASIC customers have access to a broad selection of complex digital and mixed-signal cores for system-level integration. ASIC families include support for macros including microprocessor and digital signal processing (DSP) cores, embedded read-only memory (RAM), serial interface cores, analog/digital (A/D) and digital/analog (D/A) converters and other specialized cores for internetworking and 3D graphics applications. NEC's proprietary MPU cores, such as the V830(TM), V30MZ(TM), V850(TM) processors and third-party cores such as ARM are also supported. NEC's embedded DSP offering includes both the company's proprietary SPRX core, and the Oak and Pine DSPs from DSP Group. Bus controllers, including IEEE1394, USB and PCI are also available as core cells.
Special functions for internetworking applications include 10/100 Ethernet (physical interface layer) PHY and media access interface (MAC) cores, ATM segmentation and reassembly (SAR) and MAC, asymmetric digital subscriber line (ADSL) and very-high bit rate digital subscriber line (VDSL). Graphics cores are also supported by the libraries, including specialized Phase-Locked Loops (PLLs), Rambus ASIC Cell, and 2D/3D accelerators. Providing users with optimal memory options, NEC offers compiled SRAM cores.
An embedded DRAM core based on 0.18- and 0.25-micron process technology will also be available in the enhanced ASIC library in October 1998. This DRAM core emulates standard off-the-shelf SRAM devices to operate at 133MHz and 2.5V. The core is designed to be modular, enabling it to be configured in several ways: up to 32Mbit of 1Mbit step and from X8 up to X256 in bit width. Both the 0.18- and 0.25-micron libraries will also include a new Direct Rambus(R) ASIC Cell (RAC) macro of 0.25 micron to increase the bandwidth to 1.6Gbytes/sec.
As NEC has been concentrating on multimedia applications, there will be new application-specific ASIC cores to address the merging of computing, networking and consumer audio-visual technologies. The new ASIC cores for PC computing include both an IEEE-1394.a Link and an IEEE-1394.a 400Mb PHY, while application extensions include OHCI and SBP2. For the networking and consumer audio-video domain, Ethernet MAC and PHY, as well as a JPEG decompression macro, will be offered.
Driving the SOC Business
In order to successfully merge such a wide variety of system IP cores and microprocessor cores, NEC has defined an NEC-standard system-on-a-chip bus. NEC's effort to accumulate reusuable cores to meet system-on-a-chip market demands has paid off. In order to continue this success, NEC has now added dedicated groups called "IP Frontiers" that have been chartered with transforming microprocessors to ASIC cores as well as developing and proliferating application-specific system IP.
Packaging
NEC Corporation's internal package development groups have created several packages to support the 0.15- and 0.18-micron (drawn) families. With a pad pitch of 30 microns, NEC offers the following package types:
PACKAGE TYPE MAXIMUM PIN COUNT
Plastic BGA 672
Tape BGA 696
Advanced BGA 832
Quad flat pack 376 (0.4 mm pitch)
Flip-chip 3000
Chip scale package 500
The tape BGA and PQFP packages use a tab tape to connect the die to the package, and then encapsulate the tape inside the standard package. This allows customers access to both the small silicon size enabled by the narrow pad pitch, as well as the standard packaging footprints. The chip-scale package uses solder balls at a 0.5-micron pitch and provides a package size close to the die area. Flip-chip packages utilize flip-chip bonding technology to attach the die to a substrate.
Design Tool Support
To create a design flow optimized for these advanced designs, NEC offers its ASIC customers the OpenCAD(R) Design System. To support 0.15- and 0.18-micron designs, OpenCAD will introduce a modular hierarchical design procedure, where each module is managed by a front- to back-end design flow, together with RTL-level design planning. This allows for modules to be reused. The OpenCAD design system will also incorporate a solution of signal integrity check problems posed by 0.18um/0.15um technologies.
The OpenCAD system is a unified front-to-back-end design environment that allows designers to mix and match tools from some of the industry's most popular third-party vendors. This integrated collection of tools performs design functions such as hardware/software co-simulation, cycle-based simulation, timing-driven place and route operations, cycle-based simulation, static timing analysis, and VITAL (VHDL Initiative Toward ASIC Libraries) standard sign off support.
Pricing and Availability
The aluminum and copper versions of the 0.18-micron and 0.15-micron products are scheduled to be available in October 1998, with mass production slated for Q2 1999. Copper-only versions are slated to begin sampling Q4 1999, with mass production expected to follow in Q1 2000. For a five-layer, 7-million-gate (usable) device in a 696-pin tape BGA package, pricing will be approximately $410 per unit in quantities of 10,000 per month. For a five-layer, 3.5-million-gate (usable) part in a 696-pin tape BGA package, pricing is expected to be $190 per unit in quantities of 10,000 per month.
About NEC Electronics Inc.
NEC Electronics Inc., headquartered in Santa Clara, Calif., designs, manufactures and markets an extensive line of electronic products, including ASICs, microprocessors and microcontrollers, 3D graphics accelerators, digital signal processors (DSPs), memories and components including flat-panel displays and lithium-ion batteries. The company operates a 709,000-square-foot manufacturing facility in Roseville, Calif. NEC Electronics is an affiliate of NEC Corporation (NIPNY), a $41 billion international manufacturer of computer, communications and semiconductor products. For more information about products offered by NEC Electronics Inc., visit the NEC U.S. Website at nec.com.
NOTE: NEC, V830, V30MZ , V850, VR4100, VR4300 and VR5400 are either trademarks or registered trademarks of NEC Corporation in the United States and/or other countries. OpenCAD is a registered trademark of NEC Electronics Inc. MIPS is a registered trademark of MIPS Technologies Inc. PentiumPro is a trademark of Intel Corporation and Rambus is a registered trademark of Rambus Inc. All other trademarks are the property of their respective owners. |
