Shane,
Talking about yields and our previous mentions of the importance of EDA tools and the idea that it's not that easy to make a SOC got me to thinking it might be helpful to have a concise description of what's involved in the design and production of an IC. This has nothing to do directly with the stock price of LSI, but I thought you and possibly others might be interested in how the product is made, if you don't already know. And I hope it helps to shed a little light on the complexity of the process and what all besides the demand for the product really has to go right for a design to work. Those who are more intimate with the design process or otherwise have more experience, please feel free to correct my errors and omissions.
The design, of course, starts out as a market-driven idea; a customer, or Wilf, or someone else says wouldn't it be great to have a chip that would do X, and by Jove, I think LSI just might be able to make one. They throw together a team of design engineers into a dark hole with some workstations and a few snacks, and boom, six months or a year later, out pops a design. Actually I never was a design engineer, but I do know that they use their creativity and training and EDA tools to turn the idea into the gates, latches, and registers that make up the "Logic" part of LSI Logic. Then the place-and-route tool (another EDA tool) turns these digital and analog logic concepts into a collection of interconnected transistors at specific locations. This produces a layout and netlist which simulate the behavior of the chip and are checked for functionality (using an EDA tool). They then have to be verified (by an EDA tool) against a set of design rules specific to the kind of design and especially the fabrication process. The layout is a collection of layers of polygons which describe the chip physically. The netlist contains the information which describes the chip electrically. The design rules specify things like the size of the transistors and the width and spacing of the interconnecting wires. The netlist and layout are computer files which are many megabytes or sometimes even a gigabyte or two in size. Once the design is verified, the layout file is sent to the photomask company for generation of the masks. There can be typically up to 16 to 20 masks per design. These masks are then sent to the fab and each one is used to generate a layer or layers of the design on the silicon wafers, using photolithography. The pattern from the mask is repeated on the wafer, using step-and-repeat equipment (steppers) and exposing nine (or sometimes four) chips at a time, until the whole wafer is done. A wafer typically holds a few hundred chips. The chips on the wafer are then "probed", or tested, to determine whether they are good or bad. This is done using a test pattern which was generated (using an EDA tool) during the design process. There are several different basic methods of testing, but in general they give the chip certain sets of inputs and check to see if the expected outputs are generated by the chip. This test typically takes a few seconds per chip and may take as long as a minute. The bad chips are marked with a dot of ink. The wafers then go to the packaging company, where the wafer is sawed, or "diced", into the individual chips, and the good chips from wafer test are put into plastic or ceramic packages which protect them from the environment and facilitate connection to the printed circuit board they will placed on in the eventual application. These packaged chips are then tested for a final time ("final test"), put in a tray and a box, and shipped to the customer for that revenue we all like to see (once all the debug of a new design has been done).
G.P. |
