International Conference on Consumer Electronics June 2-5 in L.A. Click on the "Conference Timetable." There's lots of info at this site:
icce.org
One example:
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DTV VIDEO
DECODERS
Chair: C. Bailey Neal, Thomson R&D Laboratories, Indianapolis, IN
Co-Chair: Michael A. Isnardi, Sarnoff Corporation, Princeton, NJ
4.1 MP@HL MPEG2 Video Decoder for Consumer ATSC
Receivers
M.S. Deiss, Thomson Consumer Electonics, Indianapolis, IN
Basic architecture and many unique features of a new single chip
MPEG2 video decoder and format converter IC are described. It
provides output resolutions as high as 1920x1080 for high definition TV
receivers down to 720x480 for set-top boxes.
4.2 A Single-Chip HDTV Video Decoder Design
L. Phillips, E. Brosz, R. Meyer, R.T. Ryan, R. Sita, Panasonic AVC
American Laboratories, Inc., Burlington, NJ
Development has been completed for a single-chip MPEG2 Main
Profile @ High-Level Video Decoder that decodes and displays all 18
ATSC digital video formats, including HDTV. Applications include
digital TV receivers, set-top boxes and computers.
4.3 Symbol-Parallel VLC Decoding Architecture for HDTV
Applications
S-O. Bae, K-S. Kim, LG Cooperative Inst. of Technology, Seoul,
Korea
A new VLC (Variable Length Code) decoding architecture is presented
where multiple shorter codes are decoded in parallel while longer codes
are processed in each cycle. This results in a high throughput VLC
decoder with minimum hardware overhead.
4.4 A Minimum Drift 3-Layer Scaleable DTV Decoder
A. Vetro, H. Sun, P. DaGraca, T. Poon, Mitsubishi Electric ITA,
New Providence, NJ
This paper describes new techniques for implementing a low-cost video
decoder that can decode an HDTV bitstream and display the signal at
lower resolutions. A new architecture is introduced through the
derivation of a minimum drift motion compensation scheme.
4.5 A Novel Memory Compression System for MPEG-2
Decoders
U. Bayazit, L. Chen, R. Rozploch, Toshiba America Consumer
Products, Inc., Princeton, NJ
A low-complexity memory compression scheme is described for
MPEG-2 decoders. The algorithm can be implemented with minimal
hardware and can be utilized to reduce decoder memory requirements
up to 50% with no distinguishable loss of image quality.
4.6 A Novel Adaptive Vector Quantization Method for Memory
Reduction in MPEG-2 HDTV Decoders
D. Pau, R. Bruni, SGS-Thomson, Agrate Brianza, Italy; A.
Chimienti, M. Lucenteforte, CSTV-CNR, Torino, Italy; R. Sannino,
SGS-Thomson, San Diego, CA
A novel method to reduce, in a scaleable fashion, the memory needed in
an MPEG-2 HDTV decoder architecture is presented and discussed.
The total amount of memory is reduced from 96 to 32 Mbits while
preserving good picture quality.
4.7 An MPEG Decoder with Embedded Compression for Memory
Reduction
P.H.N. deWith, Univ. of Mannheim, Mannheim, Germany; P.H.
Frencken, Philips Semiconductors, Eindhoven,The Netherlands;
M.v.d. Schaar-Mitrea, Philips Research Labs, Eindhoven, The
Netherlands
We present an MPEG decoder with reduced system costs by employing
embedded compression of the reference frames which are used for
motion-compensated (MC) decoding. The compression features simple
recovery of (MC) block data, while preventing visible artifacts. |
