Steve & Scumbria,
Cyrix, however plans to go another route. Instead of installing an L2 cache, executives at the company decided to move the memory controller onto the processor to reduce latency. Additionally, with the rollout of the MII 350 processor and the MII 400 processor, the company will be changing bus speeds to a 100 MHz. Says Swearingen, "Our goal is to make memory look like L2 cache. Why would you need L2 cache if you can maintain fast access times to the main memory?"
techweb.com
So, this gets back to the question I was asking about the obsolesense of cache, and it appears that Cyrix is asking the same question. Scumbria, I suppose that putting the memory controller on-chip reduces the latency, but not to the point of using high speed cache. It also seems that as the size of the blocks that need to be read from memory increase, the latency becomes less of an issue and bandwidth becomes more important.
Pravin. |
