SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : CYRIX / NSM
NSM 18.270.0%Jul 31 5:00 PM EST
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Pravin Kamdar who wrote (27132)6/6/1998 1:34:00 PM
From: Steve Porter  Read Replies (2) of 33344
 
Pravin,

Re: L2 cache vs. Main Memory.

There are a couple of thing you have to look at when it comes to memory subsystems and I will try to sumarize them here. (Scumbria feel free to jump in)

First of all if you were to eliminate L2 cache and had a "high" speed main memory system there are a couple of things you would have to remember.

Let's take cyrix's approach for example. First they want to move the memory controller into the chip. This will reduce some of the latency. In addition there would be savings in terms of look ups because you don't need to see if the data is in L2. So it may well balance.

Now the problem is the first byte penalty of main memory. I'm not sure whether the moving of the memory controller and the elimination of L2 cache balance against the initial penality, but by the sounds of what Cyrix is saying, it may well.

Scumbria, your thoughts?

Steve
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News