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Technology Stocks : CYRIX / NSM

NSM 18.27

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Jul 31 5:00 PM EST

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To: Scumbria who wrote (27178)	6/8/1998 12:38:00 AM
From: Joe NYC	Read Replies (2) of 33344

Steve, In a multiprocessor system an onboard memory controller does not make sense. Instead you want to have very large L2 caches to minimize traffic on the system bus. In a multiprocessor system, it would be nice to have 2+ CPUs share one memory controller and one very large L2 cache. With 2+ CPUs, each one it it's own packaging, each CPU needs to check all of the L2s (if I understand it correctly) before it accesses the DRAM. So more CPU's with their own L2's will generate a lot of trafic on the system bus. If anybody understand's this better, please feel free to jump in. Joe

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