Steve, <Slot1/2 vs. SlotA> Just a coulpe of remarks:
You both are confusing several things. When talking
about a bus, people usually mean three things (in
reverse order of complexity):
1. Mechanics. It is well known that the K7 will utilize
the same connector, old EISA-style, to keep cost down;
2. Electrical parameters. Here goes the GTL+ vs. EV6
something. The GTL+ require an extra power supply for
Vref, and lots of additional pins to evenly distribute the
reference. I believe the EV6 electrics do not need this
(could be wrong though).
3. Logical protocols: data/address partitioning, clocking,
transaction protocols. For your information, the P6
"split-transaction bus" was described in enough details
a few years ago, and published in 1996 (Intel order
# 242690), Chapters 3, 4, and 5.
With regard to EV6 protocols and how "big" is a jump
to 266/333MHz: let me assure you that the jump is
bigger than you seem to think (in terms of technical
implementation for Slot1 design), but you should not
worry about that - the DEC-patented clock-forwarding
technique will do the job just fine.
On a general note, since there is a consensus that the
ideas of the split transactions and non-blocked backside
caches were "borrowed" from earlier DEC designs, I
would safely assume that the newer DEC design (EV6) could
not be a step back, only forward, right? Therefore, the
EV6 bus must be advanced just by historical reasons.
(Let me discount here the Celeron design precedent:):))
And the last:
<However I don't have the documents in front of me
now to dig up the details.> - to make your assessment
of the EV6 bus more credible for Intelafelons, do
not forget to mention your NDA ## :) :)
Have a nice day. |
