Any comment on this, and how it will impact PRIA and ASYT?
Researchers Say Method Slashes Process Cost
(06/08/98; 10:42 a.m. ET)
By Yoshiko Hara, EE Times
A research group at Tohoku University, in Sendai, Japan, has
proposed a concept for semiconductor-fabrication lines that
could lower the total cost for semiconductor processes to
one-tenth of their current levels. The concept was presented at
the Semicon Kansai '98 conference, held in Osaka, Japan, June
3 to 5.
The group, led by professor Tadahiro Ohmi, developed several
key technologies to improve and streamline
semiconductor-manufacturing systems, from a new cluster tool
structure to an ability to recycle gas and liquid.
Ohmi proposed a 3-D structure for cluster tools as a part of the
new concept for a chip production line. By laying out process
chambers on a transfer changer, the cluster tools no longer
need gate valves, through which wafers are taken into
processing chambers.
The cluster tool would occupy about 1 square meter on the
floor, whereas a conventional cluster tool with four process
chambers for 200-millimeter wafers has a footprint of about 4
square meters, for example.
When the structure is applied to equipment for 300-mm wafers,
the footprint will be 1.4 meters square, or about half the space
required for current 200-mm wafer equipment.
"This means existing clean rooms for 200-mm wafer lines can
be used as it is for 300-mm wafer fabrication," said a researcher
of the group.
Several equipment manufacturers, including Tokyo Electron,
are cooperating with the Ohmi group to implement the concept
on actual manufacturing equipment. "It will take at least six
months to implement the new concept to the system," a Tokyo
Electron spokesman said. |
