Paul, re:<Why is AMD designing the K7 on the Slot A bus?>
Above 400 MHz CPU clock, 100 MHz access to L2 cache is too slow. The first solution to this problem is K6-3, which puts L2 cache on the chip running at CPU clock, equivalent to Intels kilobuck Xeon chips.
But access to main memory must be faster than 100 MHz at CPU speeds of 500 MHz and up, so the longer term solution is a faster bus.
Why SlotA instead of Slot1?
1. SlotA is or will be an open standard and yes, I believe it will be free to IDT, NSM, SGS, DEC/CPQ, MIPS, Sun and others. Last time I heard, Intel was not allowing anyone else to use Slot1.
2. Slot1 technology for memory interface (GTL+) is, I believe, just using differential voltage technolgoy, i.e., two wires for each address/data line. I understand SlotA uses "clock forwarding" in addition to this. If you can provide additional details on either of these bus technologies, I'd love to read about it. I doubt that this clock forwarding technology matters until speeds are above 600 MHz, but the Alpha chip is almost there already.
3. The thing that gives Slot1 a performance advantage over Socket 7 (but hardly over Super7) for a given CPU core is the backside bus (BSB) to the L2 cache, but Intel doesn't have any unique patents or designs in this area. For example, IDT and AMD's chips with the internal L2 cache will all implement the BSB inside the core chip, rather than external to the core chip as Intel does.
Very unlike you to ask a question that does not include the words, "profits" or "Jerry."
Petz |
