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Technology Stocks : Intel Corporation (INTC)
INTC 43.75+0.6%Dec 3 3:59 PM EST
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To: andy kelly who wrote (59560)7/10/1998 1:39:00 AM
From: Yousef  Read Replies (4) of 186894
 
Andy,

Re: "Much emphasis was placed on the "fact" that AMD's die size for comparable
chips was much smaller ... If so, why is it?"

I don't have "hard data" on AMD's K6/K6-2 die size, but everyone on the
AMD thread claims the AMD die size is smaller than Intel PII die size.
The die size is directly affected by the Design Rules (DR's) which dictate
such things as minimum linewidth/spacing, enclosure of contacts and spacing
of contacts to poly/metal. These rules are different for each .25um process !!!
AMD's .25um process also has a local interconnect level (which Intel does not have)
and this level allows "tighter packing" of FET's particularly in SRAM layouts.
The other factor that will affect the size is the CPU architecture (amount
of on-board SRAM cache, ...). Obviously the advantage of smaller die size
is that you will print more potential good die per wafer ... However, the
local interconnect adds complexity to the process with the potential of
lower yields. Intel's .25um process has focused on device performance,
minimum linewidth/space at trench, poly and metal 1 and a simpler process
that will give high yield. I expect to see Intel get more aggressive with
"tightening" the DR's for the .18um generation.

Hope this helps.

Yousef
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