Paul, <doesn't that imply the K6-2 is "worse than lousy"?>
No, it does not. I will try to explain.
From the technical/architectural point, the
performance of Pentium-II core is predetermined, and it's
top performance (per MHz of CPU core frequency) was set by
Pentium-Pro few years ago. Everybody knows the performance
of all PPro-based future Intel's CPU. That is why I was
able to predict within 1-2% the performance of new
Deschutes and weak impact of SDRAM for Intel's systems.
It does not matter too much
how do you slice caches - there is nothing to improve.
Intel cannot change core significantly - it is a major
redesign; their pipeline is already long and simplified to
full extent. All these permutations of proprietary cache chips
make only one thing - slightly faster top speed: 400-450,
maybe 500, depending on cache speed.
AMD has more advanced core - K6, it can run more
instructions per clock. However, historically
AMD has to harness its power into the existent Socket7
infrastructure in order to get any market share. Most
people do not realize that the Socket7 is currently
implemented in it's cheapest form: L2 is only one way
associated, and both L2 and main memory share the same bus,
blocking each other during operations.
When AMD will introduce the K6-3 with on-chip 256kb of L2
cache working at core frequency (300-400MHz), the game will
change, and the superiority of the K6 superscalar core will
show up. The Mendochino is essentially the PPro on a single
chip, due to process shrinking, nothing more. It will lose.
IMHO. |
