<<Does anyone know why the bottom fell out this morning>>
Cadence news maybe ?
Cadence Advances Revolutionary Timing-Driven Design Flow
Breakthrough Multi-Tool Flow Uses Advanced Constraint-Interpretation
Technology for Greater Accuracy, Faster Cycle Times at 0.35 Micron
SAN JOSE, Calif., July 27 /PRNewswire/ -- Cadence Design Systems, Inc. (NYSE: CDN) today announced a new, multi-tool timing-driven design flow that addresses the remaining technical obstacles preventing the widespread adoption of timing-driven physical implementation methodologies for deep-submicron (DSM) designs. The patented approach combines a new method of constraint passing with advanced timing-driven design planning, placement, routing, and physical optimization algorithms.
This new approach, the Cadence System-Level Constraint Timing-Driven Design Flow, is delivering greatly improved chip performance -- typically 20 percent faster clocks and as much as 6X improvement in design turnaround times, with substantially smaller memory and disk-space requirements -- in early trials with NEC and other customers. Design teams at these companies are routinely achieving first-pass timing closure for complex 0.35-micron (and below) process designs. More information about the flow is available at: http:// www.cadence.com/software/DeepSubmicron/tdd/.
"Extremely complex DSM designs are being completed four times faster and with 20 percent faster clocks thanks to Cadence," said Dr. Hitoshi Yoshi, chief manager, System ASIC Division, NEC. "This potentially means we can accelerate the sign-off-to-silicon cycle for our customers, and getting their products to market faster and having greater turnover in our fabs, thus increasing our production capacity."
Echoing this sentiment is Dan Ehrlich, manager, CAD Development Engineering for Motorola SPS: "We've been working with Cadence over the past six months to develop and qualify the System-Level Constraint Timing-Driven Design Flow. The approach Cadence is taking makes a lot of sense. We're looking forward to using this flow on some of our more challenging designs in the near future."
"The industry has been talking about timing-driven physical design for years," said Bob Wiederhold, vice president and general manager, Cadence Deep Submicron Business Unit. "But the truth is that due to the technical limitations of existing approaches, design teams have struggled to put these methodologies in place and only a few have succeeded. We expect to dramatically change that situation with this revolutionary and technically superior solution."
DSM Requires New TDD Method
Existing timing-driven flows employ either standard-delay format (SDF) path constraints, timing reports from synthesis, or both to define timing constraints for place and route. These flows have inherent limitations stemming from their inability to scale with rapidly growing DSM complexities, leading to unpredictable and suspect timing results. The main flaws are lack of timing coverage and the mishandling of timing exceptions, causing designers to spend days or even weeks iterating between synthesis and layout to achieve timing closure.
The System-Level Constraint Timing Driven Design Flow consistently uses system-level constraints, specified by the designer in the industry-open, general constraint format (GCF), to represent chip and block-level timing throughout the flow. Cadence has patented a set of "stage-based" algorithms that are generated by Pearl, its embedded timing analysis engine, and then read, analyzed, and acted upon by each tool in the flow -- design planning, place and route, physical optimization, extraction, and clock-tree design -- ensuring that consistent and complete timing information is available at each step of the design.
The Cadence presence in both the front-end and back-end of design makes the flow possible, and relies on the following Cadence software products: Silicon Ensemble(TM) DSM and Gate Ensemble(R) place-and-route software, Pearl(R) static timing analyzer, Logic and Physical design planner, CTGEN clock-tree generator, WARP router, QPlace placement engine, and PBOpt placement-based optimizer.
The new System-Level Constraint Timing-Driven Design Flow is available now from Cadence.
Consulting Services Now Available
To accelerate the adoption of the new System-Level Constraint Timing-Driven Design Flow within customer environments, Cadence Consulting Services offers a full range of education, flow, and methodology transition services tailored to this new timing-driven design approach.
About Cadence
Cadence Design Systems, Inc. provides comprehensive services and software for the product development requirements of the world's leading electronics companies. Cadence is the largest supplier of software products, consulting services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronic-based products. With more than 4,000 employees and 1997 annual sales of $916 million, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif. and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services may be obtained from the World Wide Web at cadence.com.
Cadence, Gate Ensemble, and Pearl are registered trademarks, and the Cadence logo and Silicon Ensemble are trademarks of Cadence Design Systems, Inc. All others are properties of their holders.
SOURCE Cadence Design Systems, Inc.
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