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Politics : Formerly About Advanced Micro Devices

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To: Paul Engel who wrote (35136)	7/29/1998 12:17:00 AM
From: Maxwell	Read Replies (2) of 1572729

Dr. Engel: <<< The BARRIER FILMS required to encapsulate the copper - to prevent diffusion into the oxides and bulk silicon - CONSUME SIGNIFICANT AMOUNTS OF SPACE/VOLUME that should go to copper.>>> You are completely WRONG! The barrier layer is TaN. The sidewall coverage is 50A! <<<If this is such a "cakewalk" for AMD - why hasn't AMD implemented it - and why did they have to go to Motorola for the copper process?>>> Again, you are don't understand the whole picture here. Low K dielectric is NOT NEEDED till you reach CLOSE TO 1GHz! K6 at 350MHz and PII at 450MHz are front end gate limited, not backend. There is no need to go to expensive fluorinated HDP unless you are backend limited. Sorry to disappoint you but I already did all my homework. Maxwell

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