Formerly About Advanced Micro Devices Message Board

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Politics : Formerly About Advanced Micro Devices

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To: Adrian Wu who wrote (35470)	8/3/1998 11:38:00 PM
From: Elmer	Read Replies (1) of 1574046

Re: "The problem with the P6 bus protocol is that it cannot support an L2 cache on the "frontside" bus. " Adrian, please provide data to backup this claim. I see nothing whatsoever about the P6 bus protocol that would disallow L2 cache on the MB, assuming there were no L2 already on the Die/Slot/Package, in which case it would be L3. You may be confusing bus protocol with chipset support. Currently no chipset provides caching support but there is no reason why one couldn't. Re: "please explain why the VIA MVP-3 chipsets sell for $25 when the 440BX chipsets sell for $65? " You mean you can't figure that one out? EP

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