Formerly About Advanced Micro Devices Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: Elmer who wrote (35477)	8/4/1998 5:38:00 AM
From: Adrian Wu	Read Replies (1) of 1574122

"I see nothing whatsoever about the P6 bus protocol that would disallow L2 cache on the MB, assuming there were no L2 already on the Die/Slot/Package" Why did Intel not include the option of a MB L2 for the 440EX chipset which was designed for the cacheless Celeron? The reason is because the P6 bus protocol was designed to have a separate bus for the L2 cache ("backside bus"), and not designed to accommodate an L2 on the frontside bus. Otherwise, it would make perfect sense for Intel to design the 440EX with an L2 cache option to improve the dismal performance of the Celeron. Adrian

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next