Philips is still touting its TriMedia media processor...........
eet.com
Philips plans 64-bit TriMedia processor
By Peter Clarke
SUNNYVALE, Calif. - While Chromatic Research Inc. has
abandoned its very long-instruction-word approach to graphics
processing, its main media-processor competitor, Philips
Semiconductors, is still waving the VLIW flag.
Papers to be presented by Philips at two upcoming technical
conferences maintain that a VLIW compiler-and-chip architecture
works just fine for digital TV and graphics, and can work even better
by using multislot operations and 64-bit words. The company's
VLIW architecture, known as TriMedia, is already aimed at DTV.
At the conferences Philips will lay out its second-generation
TM-2000, and detail plans to take the TriMedia to 64-bit word
lengths. It will also describe ways to improve the multimedia
capabilities of its "five-slot" instruction architecture, to be used in a
third generation of 64-bit TriMedia devices that are scheduled to
appear toward the end of 1999.
On Aug. 18 at the Hot Chips conference in Palo Alto, Calif., J.T.J.
van Eijndhoven and Frans Sijstermans of Philips Research
Laboratories (Eindhoven, Netherlands) will present "Novel
Multimedia Instruction Capabilities in VLIW Media Processors."
On Oct. 13 at the Microprocessor Forum in San Jose, Calif.,
Sijstermans will unveil the 64-bit successor to the 32-bit TriMedia.
This is destined to be the core of two processors, one aimed at
high-end videoconferencing, the other at DTV.
Multiple slots
The TriMedia architecture issues a VLIW instruction every clock
cycle; each instruction includes up to five operations in dedicated
slots within the long word. Compiler technology is used to minimize
the "no op" slots and maximize throughput.
The multislot scheme grew out of research into improving the
instruction set, particularly in areas relevant to graphics processing,
like data matrix manipulation. Attempts to do that resulted in some
operations having three or four argument registers and/or two result
registers, which is beyond the scope of a single slot. By allowing
operations to occupy two or more slots, the functional units
dedicated to each slot can connect to the multiple register-file read
and write buses.
According to an abstract of the Hot Chips paper, the overhead for
adding this flexibility is almost zero in terms of cycle time and silicon
area. Similarly, there is almost no overhead in a shared reference file.
Multislot processing and the move to 64-bit word lengths represent
two elements in a three-pronged strategy to raise VLIW
performance. The third is improvements in process technology to
increase clock frequency.
Ron Baker, marketing program manager for TriMedia, said that
while the second-generation TM-2XXX devices are at 0.25-micron
process geometries, doubling performance over the first generation,
third generation, chips will go to 0.18-micron CMOS and 300-MHz
clock frequency. |
