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Politics : Formerly About Advanced Micro Devices
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To: Elmer who wrote (35515)8/5/1998 11:11:00 AM
From: Scumbria  Read Replies (1) of 1573954
 
On a page miss, the selected ras line is already low and therefore must go high and low again to latch a new row address. On a row miss, a different ras line is selected, one that is already high, and all it has to do is go low. Different latencys here.

Elmer,

Unlike EDO, SDRAM memory controllers generally keep one page open per bank. The scenario you are describing will never occur with SDRAM. Dram accesses will either hit an open page or require precharge.

Scumbria
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