LATTICE SEMICONDUCTOR INTRODUCES 2nd-GENERATIONIN-SYSTEM PROGRAMMABLE COMPLEX PLD FAMILY
February 12, 1996, 2:39 PM EST
ispLSI 1000E Family Pushes CPLD Performance to 7.5 ns / 125 MHz While
Increasing Logic Functionality and Routability
HILLSBORO, Ore., Feb. 12 /PRNewswire/ -- Lattice Semiconductor Corporation(R) (Nasdaq: LSCC) today announced production availability of the newest generation of its In-System Programmable (ISP(TM)) High Density Programmable Logic Devices (PLDs), the ispLSI(R) 1000E family. Utilizing Lattice Semiconductor Corporation's (LSC) In-System Programmable UltraMOS(R) technology, the ispLSI 1016E, 1032E and 1048E set a new standard for High Density PLD speed and functionality. The 2,000 gate 44-pin ispLSI 1016E offers a maximum operating frequency (Fmax) of 125 MHz while the 6,000 gate, 100-pin ispLSI 1032E-90 operates at 90 MHz. The 125 MHz device also supports pin-to-pin logic delays (Tpd) of 7.5 ns while the 90 MHz device supports a 10 ns Tpd. The 8,000 gate, 128-pin ispLSI 1048E-80 provides an Fmax of 80 MHz and a Tpd of 10 ns. The new family now provides faster, pin-compatible upgrades for existing ispLSI 1000 designs. In addition, significant enhancements have been made to the earlier architectures by increasing internal signal routing resources and adding dedicated Output Enable pins.
This new family of in-system programmable logic devices is Lattice Semiconductor's second generation while other PLD suppliers are struggling to bring out their first," stated Stan Kopec, LSC Director of Corporate Marketing. "Having a high density, 125 MHz family of ISP devices means that our customers' fastest system designs can now enjoy the convenience and cost savings of Lattice Semiconductor ISP devices. The enhanced routing resources in the new family also means that designers will be able to route a greater number of complex logic designs without manual intervention."
Each ispLSI 1000E device contains a collection of programmable Generic Logic Blocks (GLBs), a unique Product Term Sharing Array (PTSA) for logic efficiency, multi-clock support and fast, deterministic programmable signal routing. A GLB can implement up to four registered or combinatorial logic functions. The ispLSI 1016E contains 16 GLBs, the ispLSI 1032E contains 32 GLBs and the ispLSI 1048E contains 48 GLBs. The new family employs an enhanced Generic Routing Pool (GRP) that doubles the potential routing paths into each GLB compared with the ispLSI 1000 family, giving improved routability that results in higher logic utilization and better routing with fixed pin assignments. Each device also has a series of dedicated inputs, bidirectional I/O pins plus 2 dedicated Output Enable (OE) pins, another enhancement on the ispLSI 1000E. Device outputs also have independent programmable output slew rate control that allows signal
switching rates to be adjusted to minimize EMI and overall system noise.
Lattice Semiconductor pioneered ISP devices 4 years ago in its ispLSI 1000 product family. The ispLSI 1000 product family has propelled Lattice Semiconductor into the position of fastest growing High Density PLD supplier with 1995 LSC High Density PLD sales approximately 3 times those of 1994. Lattice Semiconductor's ISP products allow one or more devices to be programmed on a p.c. board through a simple five-wire, 5V serial interface that does not require
special high-voltage power supplies. Today, ISP technology has emerged as the new standard for PLD technology preferred by system designers because of its ability to reduce system development time, enhance product features, minimize manufacturing costs and simplify product field upgrades.
The ispLSI 1000E family is supported by a broad range of design tools including LSC's proprietary PC-based pDS(R) software as well as third-party tools on both PC and workstation platforms. pDS+(TM) Fitters support logic design in a wide variety of design environments
including Cadence, Data I/O, ISDATA, Mentor Graphics, OrCAD, Synopsys and Viewlogic. |
