Anthony,
Great find. I found this most interesting (as Steve also pointed out):
But Intel has thoughtfully opened a fourth alternative for the company, according to Swearingen. "With the advent of
Socket-370, everything changes. Here is an interface that is inexpensive and implementable. And because it uses
GTL-type levels, it can go 133 MHz or more - much faster than Intel is pushing it. We are actively looking at that."
Intel doesn't want to push the core clock speed or the bus frequency too high on their 370 based Celerons because it would challenge the performance of their bread and butter PII. Well, along comes Cyrix and says, "thank you very much." They've been handed a low cost Intel compatible socket that removes some of the socket 7 performance constraints -- while at the same time not having the limitation of having to limit the socket's performance. This could back fire on Intel big time.
As for the Jalepeno not being able to compete with a 1Ghz K7, this may be true, but Cyrix will definitely capture the low end. Without copper, low k dielectrics, and perhaps SOI, I don't see how NSM gets to 1Ghz without going to 0.13u.
On another point, I believe that performance sells. The problem is that the MII lacks performance in an important area. Who would look at Cristy Brinkley if she were missing a leg? PR rating, or no PR rating... it just doesn't matter. Performance matters. The PC rags will sort out the rest.
Finally, is anyone else getting worried that NSM is falling behind in the process war? How is NSM going to get copper and SOI at an affordable development expense? IBM already has them. AMD will get them from MOT. Intel can afford to throw enough money at any problem they need to solve. Perhaps NSM can license the new data flow architecture of the Jalepeno to IBM in exchange for process technology.
Pravin. |
