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Top EDTN Story: from Semiconductor Business News
TI plans to push 0.10 micron into production by 2001
By J. Robert Lineback
DALLAS -- Texas Instruments Inc. here today disclosed aggressive plans to begin using a 0.10-micron process technology by 2001 to produce highly integrated ICs that contain both analog and digital functions. The technology will include up to eight levels of copper interconnect, and currently TI plans to launch the process on a new 300-mm wafer fab line at its main production campus in Dallas.
While TI researchers said the aggressive schedule was not an acceleration of next-generation technology, the planned use of 0.10-micron CMOS (drawn-gate length) processes is about five years ahead of the national roadmap, published by the Semiconductor Industry Association (SIA). Most leading chip manufacturers are just now beginning to move IC designs to new 0.18-micron technologies with 0.15- and 0.13-micron expected to follow in the next several years.
Intel Corp., for example, plans to bring its 0.13-micron process technology into production around 2002--a time frame when it also believes 300-mm wafer fabrication will be feasible. Intel has not yet officially set a schedule for the launch of 0.10-micron technology, according to a company spokesman.
In making its disclosure today, TI said it is the first semiconductor manufacturer to announce the development of an IC technology for design rules of 0.10 micron and effective gate lengths (L-effective) of 0.07 micron. The Dallas company intends to release the technology for IC designs in the year 2000, with volume production beginning in 2001.
A key feature in TI's technology will be the ability to produce 0.10-micron analog and digital circuits on the same die. The process marks the first time that both analog and digital functions will be supported by a new technology node, according to Peter Rickert, senior manager of TI's technical staff and platform development manager. Historically, analog functions have lagged digital devices in the use of advanced process geometries.
With its 0.10-micron technology, TI believes system designs--such as cellular telephones--will be completely re-partitioned to include many more analog and mixed-signal functions on highly-integrated ICs. These system-on-a-chip designs will pack up to 400 million transistors on a single chip. That's about 15 million gates of logic.
A dual threshold voltage design technique for transistors will be incorporated into the technology, enabling designers to develop ICs that operate at 1-GHz using only 1 volt. With this approach, designers will be able to select either 200- or 500-millivolt threshold voltages for transistors in their designs to match power consumption and performance targets in each function block.
"DSP systems are driving this [technology need] in terms of millions of instructions per second [MIPs] but also the need for analog integration with digital," Rickert said.
TI also intends to use the technology to produce high-speed RISC processors for its foundry customer, Sun Microsystems Inc. "This process technology will enable our future generation of Sparc processor to extend the clock frequency well beyond 1 GHz," said Mel Friedman, president of Sun Microsystems' Microelectronics Division. One of the first parts to be produced with the technology will be Sun's 64-bit UltraSparc processor.
In addition to copper interconnect, the 0.10-micron technology will use low-k dielectric insulators, with the current target set at pushing the dielectric constant below 3.0 compared to 4.1 for today's conventional silicon-dioxide materials. The low-k dielectric will reduce capacitance in the interconnect while copper lowers resistance.
TI plans to introduce its first copper interconnect technology in the 0.15-micron generation and then move it into the 0.10-micron process, Rickert said. The company also intends to team the copper with new dielectrics at the 0.10-micron generation. It is currently evaluating three different dielectric materials for the 0.10-micron technology.
To produce 0.10-micron device features, TI is also planning to use deep ultraviolet lithography, based on 193-nm excimer lasers. Other chip makers are also exploring the use of other exposure technologies because some experts believe UV technology may prove inadequate around 0.10-micron feature sizes.
"We have no plans to use any exotic lithography technology," Rickert said. "We will begin evaluation of steppers in the middle of the year," he added, referring to selecting the lithography tool set for the new technology.
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