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Politics : Formerly About Advanced Micro Devices
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To: Tenchusatsu who wrote (36708)9/3/1998 2:06:00 PM
From: Ali Chen  Read Replies (2) of 1571403
 
<"whirlwind development effort" of Mendocino,

"Originally expected to ship late this year, the product was
pulled into an August release. Although most processors
take two or three tries before they can be shipped, the first
silicon of Mendocino was so clean that Intel is using it to
begin volume shipments."

Wow.

Tenchusatsu>
----------
You must be too over-exited, men. The P-ii core already
has a debugged (fully? Xeon?) controller for the
backside L2 cache, with all IO pads on the proper side.
Any EE student can glue a SRAM to this chip flawlessly.
It would be a total shame if Intel had to spin another
silicon in such a sky-rocket upgrade.

<BECAUSE THE EXTERNAL L2 CACHE IS DEADLOCKED at a
FIXED 100 MHz !
Good point. Very good point. >

Wrong point.
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