SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Tenchusatsu who wrote (36545)9/3/1998 3:50:00 PM
From: Ali Chen  Read Replies (1) of 1571156
 
Ten, <doesn't AMD use a process which adds one more layer than Intel's process? In my understanding,..>

Your understanding seems to be not quite correct.

Looking at the foil #14 from Intel:
pentium.intel.com
"... 5 Metal layer 0.25 micron CMOS".

At the same time,
amd.com reads:
"AMD's 0.25-micron, five-layer-metal process technology"
Therefore, the number of layers appears to be the same.

<...that [extra layer] will increase densities and
reduce die size, but it will also reduce yields.
Is this correct?>
As we saw from above, this is literally incorrect.
In general, for a given defect density, the smaller
die size tends to increase yields.
Even more, if you want to follow
your logic, try to replace [...] in your statement
by "Intel's 0.18um technology" , and the
argument will work against you.
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News