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Politics : Formerly About Advanced Micro Devices
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To: Tenchusatsu who wrote (36725)9/3/1998 9:31:00 PM
From: Ali Chen  Read Replies (1) of 1571225
 
Ten, <..there was a redesign of the cache controller in order to add two uni-directional data buses, as opposed to one bi-directional bus.>

First, how do you know this? I don't recall any mentioning
of this redesign in Intel's presentations.

Second, usually busses are separated inside the processor,
and a special multiplexor is NEEDED to combine the two
busses into a bi-directional one. It should be not a big
deal to remove the extra block with obvious simplifications.
Any EE graduate can do it given all the rtl files and
documentation.

<even a EE student can just "glue> is indeed an
exaggeration on my part, just for the sake of
rhetoric.

<Tell us why it's the wrong point.> Because the problem
is not in the fixed frequency but in the ability of
PII core to do several things: deferred write-backs that
do not block L2 accesses. This makes the major contribution
to P-II performance, although these features can be
implemented in a north bridge for Socket7. Long
(12-14 stages) PII pipeline also helps to decrease the
cost of L1 misses and hide the high L2 access latency.
This also explains why there is practically no
performance difference between the full and
a half-speed L2 in the P-II/PPro line.

BTW, you forgot the magical word -"please".
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