Jock,
I have wanted for a while to make some comments to this thread about standard-cell based designs. Your post finally prompted me to sit down and write down my thoughts.
First let me say that I thoroughly agree with you that LSI is going the right direction by getting out of gate array design and more into standard-cell based designs. However, the point I am going to try to make is that all standard-cell based designs are not created equal. Some can be much worse for LSI than gate arrays and some can be much better; they are not really telling us much by telling us how much of their business is from std.-cell or CoreWare based designs. I think it is almost an accepted assumption on this thread that the gate array/std. cell split tells us a great deal about prospects for design wins and good margins, but I think that assumption is wrong. I also think a more detailed explanation of the various design approaches will partially debunk another popular and contrary idea on the thread that LSI is facing or may face widespread competition even in its CoreWare designs that is going to drive LSI into the ground.
Pure standard cell designs are a poor design strategy for a company like LSI. They have a short design cycle time, which makes them attractive, but they have only modest performance. More importantly, these designs are very easy to do (hence the short design cycle time), so there is a lot of competition, making them basically a commodity, where margins are horrible. Production cost is affected by the density of the design, which is dependent on good CAD tools and process technology, which as we have discussed previously on this thread, are becoming more and more cheaply available to everyone through the foundries and companies like Cadence.
People would be right in attacking LSI's design strategy as subject to widespread competition if indeed they were producing pure standard cell designs. However, I was greatly reassured by the pictures in LSI's latest annual report. None of the important products for LSI appear to be pure std. cell designs, including the Cisco router chip, the Fibre Channel controller, the DCAM chip, the GSM processor, or the DVD decoder.
Determining from the small chip photographs exactly what design strategy LSI is pursuing is a little more difficult. A good chip design is some combination of standard cell and custom digital, hard and easy analog, and embedded memory. A high-margin, high-performance design assembles combinations of expertise that are hard to find. It does not and probably should not include all five elements at once, because the more elements you combine, especially of the more difficult elements (custom digital, hard analog, embedded memory), the harder and longer the design cycle will be.
Pursuing a pure digital design based on combinations of custom and standard cell blocks is a better strategy than standard cell alone, but it is not the ideal strategy either, because your products are constantly becoming outdated as standard cells catch up with your custom design. Custom blocks have poorer density and longer design cycle times, so when they eventually lose their performance advantage, they are worse than the pure standard cell design. So you are constantly on a treadmill trying to stay ahead of the commodity pure std.-cell guys in performance. It will give you better margins than the pure std.-cell strategy if you are successful in creating your new designs, but you had better not have a major screw up in your design cycle or you will fall disastrously behind, investing more resources into designs because you are doing them custom but getting no better margins out in the market than the commodity people because you have lost your performance edge.
A better strategy is adding analog or embedded memory to your designs in an intelligent combination with std.-cell/custom digital by assembling design and systems expertise that is not readily available to John Doe Semiconductor, Inc with his dozen design engineers and a Taiwanese foundry. At the same time you need to keep your design process under control such that you are investing resources into "doable" designs--designs that maintain a significant performance edge after all the blocks are combined and are still debuggable, testable, and manufacturable. This is, I hope, what LSI is doing, and why they have a good future ahead of them.
Regards,
G.P. |
