Michael, Tony, article...Emulator sheds early light on Merced software.
and The demo ran on a sophisticated software emulator that
mimics the complete Merced instruction set, the chip's firmware-processor
interface and its multiprocessing interrupts.
This is absolutely the right way to do extremely complex CPU design, i.e., simulate, or emulate every gate, latch, register, adder, pipeline, cache, fetch, store, instruction, interrupt, single CPU, multiple CPU, OS, diagnostics, functionally and at speed, etc., before one chip is committed to silicon. I'm happy to see Intel is going through this process and taking no shortcuts. The world class BIG CPU developing companies like IBM do it, so Intel must. Of course, it's practically a no-brainer nowadays that you must simulate everything before committing anything to silicon. Otherwise, you end up recycling a lot of chips back into sand, or something.
"We have major operating systems booting and running on this presilicon
development environment, which is a high-speed software emulator for [Merced]
that runs on an IA-32 host," said Rumi Zahir, an Intel senior architect. "It simulates
an entire IA-64 platform that includes multiple processors and the standard
platform devices, and it provides multiprocessor simulation capabilities."
This is ahead of where I would have thought Intel would be in Merced development, vs. a product release of, when, 1H00? (Looks weird, doesn't it, 1H00?). Of course, I'm not privy to Intel's milestone schedules, so, this might just be (hopefully is) "right on schedule."
Tony |
