Tony & Intel Investors - More Information on McKinley, Foster , Willamette and Colusa !
The RoadMap is a busy one !
Paul
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dailynews.yahoo.com
Thursday October 8 10:42 AM ET
On Intel's horizon: Foster, McKinley
PC Week
By Lisa DiCarlo, ZDNet
SANTA CLARA, Calif. -- Intel Corp. on Wednesday laid out its four-year road map for 32- and 64-bit microprocessors for high-end workstations and servers.
At a briefing at its headquarters here, Intel said that true enterprise customers require long-range planning and as a result it has decided to "open its books."
First, the 32-bit plans.
After the release in the first quarter of Tanner, its 500MHz chip with integrated three-dimensional instructions, Intel will work toward the next-generation 32-bit "microarchitecture," code-named Foster.
Intended for both workstations and servers, Foster will hit the market in late 2000 or early 2001 at a minimum of 1GHz, said Fred Pollack, an Intel fellow.
Although Pollack declined to provide full details about Foster, he did say it is "superpipelined," explaining that each pipeline stage in the architecture processes less work than previous architectures, and that there are more pipelines.
In addition, Foster has better branch prediction for much lower latency, and it supports a peak bandwidth of 3.2GB per second.
In contrast, today's Pentium II Xeon architecture is capable of a peak bandwidth of 800MB per second.
On the server front, Intel will provide up to a four-way Foster configuration with a chip set code-named Colusa. Modifications of Colusa will be made for two-way workstations.
Another significant piece of news is that starting with a 32-bit chip code-named Cascades in late 1999, Intel will include a minimum of 1MB of on-chip Level 2 cache on every high-performance microprocessor.
Pollack declined to say exactly how much cache the first versions of Foster will have, but it will be at least 1MB.
Although it wasn't a focus of yesterday's briefing, this microarchitecture will be offered in a chip for volume-oriented mainstream PCs, code-named Willamette.
That chip will differ from Foster in the size of cache, bus speed and multiprocessing capability.
Although he declined to discuss it, Pollack said Intel has another 32-bit microarchitecture in development, which will be a follow-on to Foster.
On the 64-bit horizon, Intel says it is on target to deliver the first samples of Merced in mid-1999. Shortly thereafter, it will deliver software development systems to third parties.
Intel is developing a four-way chip set for Merced, but Pollack said that many systems makers are working on their own chip sets, some of which will support up to a 32-processor configuration.
Merced will also be used in workstations, which are likely to cost about $9,000 and up, Pollack said.
After Merced, Intel will work toward McKinley, the second-generation 64-bit architecture.
Due for release in late 2001, McKinley will run at a minimum of 1GHz and have the largest on-chip Level 2 cache of any Intel chip, Pollack said.
More importantly, perhaps, the McKinley architecture will support a memory large enough to fit almost all databases within it, resulting in high-speed queries and other executions. McKinley will also have a super-fast I/O subsystem.
All the processors discussed Wednesday will be built on a .18 process. But in 2002, Intel will develop a lower-cost version of the 64-bit McKinley for workstations built on a .13 process.
According to Pollack, this will be the first 64-bit chip from Intel geared toward somewhat mainstream
workstations.
Pollack does not expect the transition to 64-bit computing on the desktop to occur until the majority of applications are recompiled for 64 bits, which is not expected for about five to six years.
Until today's 32-bit software is recompiled for 64 bits, the Foster platform will run 32-bit applications faster.
Finally, Intel will provide a migration path from 32-bit to 64-bit platforms in the form of a chip set that works with both Foster and McKinley servers, Pollack said.
The set will mainly provide a way for OEMs to build servers in 2001 that will accommodate either chip.
Intel had earlier expected to build motherboards with a so-called Slot M, which would accommodate either 32- or 64-bit chips, but it scrapped those plans after Merced was delayed by six months.
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