Intel outlines high-end-MPU plans -- Beyond Merced
Oct. 09, 1998 (Electronic Buyers News - CMP via COMTEX) -- Silicon
Valley- Turning the spotlight on its 1-GHz performance path, Intel
Corp. last week mapped out its high-end microprocessor strategy and
outlined plans for serving OEMs in the workstation and server markets.
During a closed briefing, company executives revealed details of two
new 1-GHz processors, both of which are due around the turn of the
century: Foster, a 32-bit follow-on to Cascades; and McKinley, the
successor to Intel's first 64-bit chip, Merced. The processors are
designed solely for workstations and servers.
As it stands now, Intel's 32-bit high-end processor roadmap extends
from the 500-MHz Tanner chip, which will be rolled out next year,
through Cascades, a processor with integrated Level 2 cache that Intel
will manufacture on a 0.18-micron process in 2000. From there, OEMs may
choose a 64-bit Merced chip in early 2000, or turn to Intel's next
32-bit offering, Foster, in 2000 or 2001.
While the Merced will be aimed at the top end of the
workstation/server market, Foster will target platforms in the $3,
000-to-$8,000 range. The entry-level workstation/server segment will be
served by Willamette, a desktop-PC-class processor that will do double
duty in higher-performance applications. Willamette-based servers and
workstations will be priced just under Foster-based systems, much the
way the Pentium II relates to Intel's current Xeon processors.
"Our segmentation strategy is designed to take the Intel architecture
from the lowest-end desktop to the highest-end server," said Fred
Pollack, Intel fellow and director of measurement, architecture, and
planning for the company's microprocessor products group.
The rare glimpse at its closely guarded roadmap shows just how far
Intel is willing to go to counter the workstation/server product plans
recently published by several competitors in the RISC microprocessor
market.
"The Intel architecture has taken a significant role in the
workstation and server market," Pollack said. "Customers expect you to
roll out a much longer roadmap. To be a very serious player, ... it was
something we needed to do."
At the end of 2001, Merced will gradually be replaced by McKinley,
Intel's first 1-GHz chip, which will also inaugurate Intel's
0.13-micron silicon process and copper interconnect design. McKinley
derivatives are expected, emphasizing performance and low cost.
Pollack said McKinley and Merced share common traits, but noted that
the McKinley chip includes updated features that double the Merced's
performance. "There were things learned in the design with Merced that
we didn't like, that we would have liked to go back to and do again,"
he said.
To improve performance, Intel increased the processor's execution
units, while shortening the pipeline, or path, through which the
McKinley's instructions process data. The device will also boast the
largest amount of integrated cache memory of any Intel microprocessor.
Intel's Foster chip, meanwhile, will redefine the company's 32-bit
processor design in much the same way the Pentium Pro and Pentium II
processors marked a new generation of Intel chips, Pollack said.
Foster will include dynamic execution and superpipelining, to help
the chip execute instructions faster, as well as a new feature called a
"trace cache." The new cache will eliminate the need to decompress the
processor's instructions, removing a step from the processing
procedure.
Compared to the 800-Mbyte/s front-side bus bandwidth achieved by
Intel's current processors, Foster's bus will run at a blazing 3.2
Gbytes/s and support two channels of Direct Rambus DRAM, Pollack said.
Foster will be used in two- or four-way servers using the upcoming
Colusa chipset, he added.
Foster, Merced, Willamette, and all succeeding Intel microprocessors
will integrate L2 cache directly onto the die. Intel's processors will
not use discrete SRAM chips as L3 cache, Pollack said, adding fuel to
analysts' belief that the SRAM cache market may be nearing the end of
its life.
Research firm In-Stat Inc., Scottsdale, Ariz., estimates that this
trend will cause the discrete SRAM market to shrink from $4.18 billion
this year to $2 billion in 2002. Even so, analysts would like to know
how Intel will find room for the megabytes of cache memory demanded by
its high-end chips.
"We've wondered how Intel is going to embed 1 and 2 Mbytes of memory
in its Xeon chips," said analyst Dean McCarron of Mercury Research,
also in Scottsdale. "We've heard OEMs talking about future systems with
1, 2, 4, even 8 Mbytes of cache."
OEMs weighing which processors to purchase will have to consider the
availability of 32- and 64-bit software before choosing their
architecture. Using 32-bit software, for example, Foster and Merced are
actually about equal in terms of their ability to calculate
floating-point operations. And McKinley will actually be slower than
Foster in running 32-bit integer calculations, Pollack noted.
Not until the release of native 64-bit software-or until 32-bit
software has been recompiled-will Intel's 64-bit chips really start to
outpace Foster.
High-end software availability will help speed the industry's
conversion away from 32-bit microprocessors, Pollack said. Intel will
also help the transition by designing different versions of an
eight-way chipset for both the Foster and McKinley chips.
As EBN previously reported, a similar transitional chipset was
designed to bridge the shift between the Tanner processor and the
Merced, but was shelved when the Merced project was delayed last
spring. When it finally goes into volume production in 2000, Merced
will be supported by OEM chipset designs that will enable up to 32
processors to run in parallel.
To get customers rolling, Intel is designing multiple versions of
chipsets supporting up to four Merced microprocessors, Pollack said.
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