High Priest:
<<I haven't figured it out yet from the minimal press releases, but does the K7 use ON-CHIP L2 cache or merely have a backside bus for addressing OFF-CHIP L2 cache?>>
It will be OFF-CHIP L2 cache just like the PII. The 128K L1 cache is divided to 64K data and 64K instruction just like the Alpha 21264.
9 issue means there are 9 "execution units". For the PII there is 5,
1 store data, 1 store address unit, 1 load address unit, 1 integer, and 1 FPU. For the K6 there is 6, 1 store, 1 load, 2 integers, 1FPU, and 1 MMX. For the K7 there are 9, 3 integers, 3fpu, and 3 address units. For the alpha 21264 there are 6, 2 fpu, 2 integers, and 2 address units.
Maxwell |
