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Politics : Formerly About Advanced Micro Devices
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To: Steve Porter who wrote (39198)10/13/1998 3:25:00 PM
From: Maxwell  Read Replies (2) of 1573849
 
Steve:

<<Wouldn't a layered scheme like I suggested in my previous post to you make much more sense as a long term design goal?>>

Probably. You have to remember that the director of K7 is a guy who
co-designed the Alpha 21264. He probably has done some simulation
already and knows what best. He has taken a lot of design in Alpha
to bring into K7.

<<How could you get around using a 2 cycle latency for an L1 of that size. >>

Now that I think about it the latency of 2 is about correct. Remember
that the fastest SRAM is currently about 2ns. At this response the
fastest speed is 1/2ns=500MHz. Thus to get the speed beyond 500MHz
higher latency of 1 is a must. Otherwise the CPU and L1 is out of
synchronization.

Maxwell
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