Ten, <Mendocino's lower-latency on-chip cache does prove that latency does matter in terms of real-world performance,>
No it does not. Please check data first,
side-by side:
tomshardware.com
(and related indexes). Mendochino and Pent-II have
IDENTICAL performance, both in business apps
and in games. Do you, by chance, confuse these
processors with Sharptooth samples?
<<OOO" instructions masking the processor bubble...
.. may be true for clock speeds up to 300 MHz...
that processor bubble larger and larger to the
point where it can't be masked anymore by
instruction-level parallelism.>>
It depends. The absolute MHz does not
matter much until
the L2 access time is in the range of
pipe length. With a good off the shelf
SRAM, even with X-3-3-3, it is still of
the order of the pipe length.
With 72 (72? did I hear it right?)
instructions waiting to
dispatch in K7, there must be something to
mask the bubble. However, there is
some caveat, as usual.
<..that larger caches, especially at the L1 stage,
usually mean longer latencies or slower clock
speeds. What are your thoughts on this, Ali?>
I do not have thoughts. I know that the Alpha
people are the best to handle the "low-tick"
design. I hope you remember that the success
of PPro core is solely indebted to ideas
stolen from early DEC Alpha.
BTW, how your digesting of K7 architecture is
progressing? |
