Ali, <Mendochino and Pent-II have IDENTICAL performance, both in business apps and in games. Do you, by chance, confuse these processors with Sharptooth samples?>
I said that Mendocino's lower-latency on-chip cache does prove that latency matters in real-world performance. You counter with a link that proves my point. How? Well, how else would Mendocino, which has a cache 1/4 the size of Pentium II's cache, be able to match the performance of its big brother? There are two possible answers: Either both latency and size doesn't matter (doesn't make sense or else K6-3 would be useless), or the improvements due to latency offset the penalties due to smaller size. In other words, latency matters in this case.
<With 72 (72? did I hear it right?) instructions waiting to dispatch in K7, there must be something to mask the bubble. However, there is some caveat, as usual. >
Even if 72 instructions were waiting to be dispatched in K7, where would the instruction-level parallelism (ILP) be found in your average x86 code? K7 adds more execution units, but they don't mean much if the ILP just isn't there.
<I hope you remember that the success of PPro core is solely indebted to ideas stolen from early DEC Alpha.>
Of course, of course. Just like Intel's upside earnings "surprise" hides the quarterly billion-dollar losses incurred due to those pesky stock options, right Ali?
<BTW, how your digesting of K7 architecture is progressing?>
It's going to take time. AMD sure did present a lot in the slides. K7 looks like a real beast, something that could perhaps surpass P6 clock-for-clock. Nothing in the slides suggests that there are any features in the K7 which are significantly behind the P6.
On the other hand, AMD seemed to take the Ford Mustang approach towards the K7 processor design. Instead of features which are totally new, the K7 simply employs more of everything. More execution units. More cache. More decoders. More branch prediction logic. More power, argh, argh! Not that there's anything wrong with that, except that I wonder whether AMD is hitting the wall of diminished returns with its "wider is better" philosophy. All this additional hardware will require more implicit ILP in programs in order to be efficient. And more ILP is awfully hard to achieve in x86, especially since programs these days aren't even keeping the P6 pipelines full.
What are your thoughts on K7?
Tenchusatsu |
