"Ten", <there are any features in the K7 which are significantly behind the P6.> Oops! An Intel employee has spoken!
With such an arrogance from bottom to top, Intel
must be in real trouble with regards to engineering:)
Re <..Intel's upside earnings "surprise" hides the quarterly billion-dollar losses incurred due to those pesky stock options,>
Eah, I cannot catch them from the published
report, but if you subtract the non-accountable
stock repurchase of $1.7B, you will end up with
only $400M in earnings (before taxes)... Sort of
a difference..
Going to technicalities:
<how else would Mendocino, which has a cache 1/4
the size of Pentium II's cache, be able to match
the performance of its big brother? There are
two possible answers:...>
You missed the third one - non-blocking
write-backs, for example :) It looks like
you still have some confusion as how the
SDRAM works :)
<more ILP is awfully hard to achieve in x86,
especially since programs these days
aren't even keeping the P6 pipelines full.>
You have hit the nail into x86 coffin, right.
You passed my preliminary examination:)
<Instead of features which are totally new,...
AMD is hitting the wall of diminished
returns with its "wider is better" philosophy.>
Your observation about "the wall" may be correct.
However, it sounds like you have something totally
new to run the x86 crap, right? Incidentally,
as all benchmarks show, Intel's P6 is not
exactly jumping over that wall with all their
attempts to shuffle caches... IMO, the
"revolutionary" Merced approach has very
good chances to fail.
-Ali
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