Ali, re: Mendocino's PII-like performance explained as <You missed the third one - non-blocking write-backs, for example>
So you're saying it's not latency, because of your dual independent bus argument. And you're saying it's not bandwidth because otherwise Xeon would show a greater performance advantage over Pentium II. Those are the only two advantages of the Mendocino on-die L2 cache over the Pentium II's off-chip L2 cache. That would suggest that all you really need is 128K of L2 cache, if your arguments hold water.
Of course, Intel decided to go with 512K of off-chip L2 cache in their consumer-oriented Pentium II when they could have gone with 256K (like PPro) or even 128K (to save money). And AMD decided that Sharptooth needs a full 256K of L2 on-die cache, instead of a simpler 128K cache. Care to reason why, or do you know something that the performance validators at Intel and AMD don't?
<Your observation about "the wall" may be correct. However, it sounds like you have something totally new to run the x86 crap, right?>
The guy who announced Intel's Foster/Willamette mentioned that this "P7" design will include, among other things, an "instruction trace cache." Took me a while to find out what the heck that thing does. It's going to take me another while to judge whether such a thing would help in the x86 world. But at least it's something new.
On a tangent, I was pretty surprised that Intel would even mention this feature of the P7 two years before its scheduled release. I know that Intel is concerned over AMD K7, but if this announcement was meant to take some wind out of K7's sails, then I don't think this course of action was pretty wise.
<Incidentally, as all benchmarks show, Intel's P6 is not exactly jumping over that wall with all their attempts to shuffle caches...>
First of all, Xeon's expensive L2 caches do make a difference when it comes to heavy transaction processing. If it didn't, then why would Intel even bother with 1 and 2 MB versions of Xeon for servers?
Second, Intel decided that Cascades and Coppermine should feature on-die L2 caches. Performance? Nah. Cost savings? If so, then you can bet that Intel's margins with Cascades will far exceed those of the K7 which features that nasty off-chip L2 cache that Intel wants to move away from.
<IMO, the "revolutionary" Merced approach has very good chances to fail.>
Why is that? Even Intel admits that Merced isn't going to be faster than Willamette/Foster when running x86 code. Merced's other uncertainties are part of a totally different subject.
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