Top Technology Story: EE Times
Chaotic PC market shapes processor road maps
By Craig Matsumoto
with additional reporting by David Lammers
SAN JOSE, Calif. — The Microprocessor Forum will kick off Tuesday (Oct.13) with a look across a landscape that's become terra incognita. The personal computer industry, long seen as a steady line of incrementally more powerful Intel X86 processors, marching — more or less unaccompanied — toward the horizon, has devolved into chaos. With its once monolithic market fractured, Intel Corp. is no longer in control. Competitors of every stripe, from historic archrival AMD to completely new ventures, are sinking their roots into a niche or two, hoping to outmaneuver the Santa Clara, Calif., giant.
In high-end servers, increasingly a multiprocessing market, Intel will hand out a few more hints on IA-64: its Merced and McKinley processors. But Advanced Micro Devices Inc. will counter with a first look at the Alpha-bused, giant-cached K7 CPU. And in perhaps the unkindest cut of all, stalwart Intel customer Compaq Computer Corp. will unveil its plans for a new, full-blown Alpha implementation, the 21364.
Meanwhile, the midrange server market is spinning off into a separate, IA-32-only segment. Stung by the growing strength of the K6 and Cyrix parts, Intel will unveil its plans for this arena as well, using new IA-32 CPUs.
"For the next couple of years, even past the debut of Merced, IA-32 will be the important architecture except for the very high end," said Michael Slater, executive editor of Microprocessor Report, the forum's sponsor.
At the low end, new entrants are scrambling to grab real estate in the only hot segment of the PC market, the sub-$1,000 arena. As Intel casts about for an answer here, ventures as diverse as National Semiconductor Corp.'s Cyrix group, Integrated Device Technology Inc.'s Centaur division and startup Rise Technology will show X86 CPUs targeted for low-cost, low-power systems. And in the background — conspicuously unmentioned at the forum — a new generation of Windows CE subnotebooks and palmtops based on RISC CPUs, with costs unimaginable in the bloated X86 arena, is gradually undermining the very foundations of the PC market.
For all of the churning in multiple segments, much of the attention at the forum will be focused on the high end. Already last week Intel began to show its battle plan. Along with Merced, the company will unleash a processor family code-named Foster for mainstream servers and workstations. The Pentium II Xeon family will be transformed into a new architecture to debut in the Foster and Willamette processors by 2001, Intel said.
Not that this is a retreat from IA-64. Merced continues to be on target for sampling next year, said Fred Pollack, a director with the microprocessor products group. In fact, Intel is working on an improved IA-64 part called McKinley, due to succeed Merced by 15 to 18 months.
Xeon will be succeeded by chips called Tanner and Cascades, and by 2001 Intel hopes to replace those parts with yet another new 32-bit X86 architecture, to debut with Willamette in the PC space and Foster in the mainstream workstation and server space. Since Merced by then will still be in a rather experimental stage, "Foster is going to be a far more important part than Merced" in terms of units sold, Slater said.
Pollack disclosed only a few details about the new architecture. Intel will be adding stages to the pipeline to increase throughput and is improving pipeline efficiency to keep instruction "bubbles" from getting stuck. Among the efficiency improvements is the addition of an on-chip "trace cache" storing entire instructions, which then don't have to be decoded when called again.
Bus bandwidth is expected to get up to 3 GHz with Foster, against a peak of around 800 MHz for current systems, Pollack said. More important, Foster and Merced will use the same bus, to encourage OEMs to migrate from Foster to Merced. "They're trying to make it relatively easy to incorporate IA-64 into people's processing plans," Slater said.
Foster will match Merced's performance on 32-bit applications and even beat it on floating-point operations, Pollack said. Merced will excel at applications exploiting 64-bit addressing, and at managing memory and I/O. The latter becomes a burden in multiprocessor machines, one reason why Intel's processors have competed weakly at the high end.
The new chips will face growing high-end competition from AMD, which will describe its K7intentions at the forum. K7 reportedly will break out of the socket-7 bandwidth bottleneck by employing huge on-chip caches and a version of the Alpha system bus licensed from Digital Equipment Corp. This will make K7 incompatible at the bus level with all Intel processors, but compatible with the Alpha CPUs now owned by Compaq. So both Foster and K7 will have bus-compatible upgrade paths into the multiprocessing server arena.
As for Merced itself, the first part is in physical layout, and Intel designers have begun looking at the chip's timing to hit their frequency targets. The company has produced a chip kernel bootable under certain flavors of Unix and an early version of 64-bit Windows NT. Merced remains on its revised schedule for sampling in mid-1999 and production roughly one year later, Pollack said.
In addition, server OEMs are working on the chip sets to place IA-64 parts in systems with up to 32 processors.
Perhaps more interesting is the McKinley chip, already two years into development, which will include what Pollack called "lessons" — improvements that couldn't be implemented in Merced without disrupting the entire design. Pollack declined to reveal frequency targets for Merced but did say they will be less than the gigahertz level targeted for McKinley.
The improvements mean that Merced will act as preamble to McKinley's debut, likely to be late in 2001.
"McKinley is going to be a more interesting processor than Merced," Slater said. "There will be [at first] systems with Merced built in modest volumes. You'll see Merced as the chip that gets the architecture started." But because companies such as Hewlett-Packard Co. and IBM Corp. seem comfortable with existing workstation and server processors, they won't shift to Merced immediately, putting the processor "at the fringe of the market" during its early runs, he said.
By 2002, Intel hopes to have McKinley and Merced ported to 0.13-micron rules. That will add performance to the high end, but it will also lower costs to allow the IA-64 parts to begin attacking high-volume markets. By then, a larger share of workstation and server vendors might be ready to shift to a new processor architecture, Slater said.
"Realistically, it's going to be years before Merced or IA-64 processors are as significant as even Alpha is today. It's probably going to be 2002 before they get there, which is a long time in this business," Slater said.
Compaq is hoping to catch Intel in midstream during this transition, offering Alpha CPUs at least as powerful as Merced, with what the company will claim to be superior multiprocessing characteristics. Compaq will describe the EV7, aka 21364, at the forum.
Meanwhile, the sub-$1,000 race will be giving Intel headaches as well. As the company appears to fumble about with a proliferation of pinouts, cacheless and cost-reduced parts, and private briefings, new ventures are flocking to the market.
IDT's Centaur will show its next-generation WinChip 4 plans at the forum, Cyrix will describe its next core, Jalape--o, and startup Rise will unveil a low-power, low-cost core, the mP6. All of these devices appear to emphasize simple, streamlined cores that can run at very high clock rates with relatively few transistors and, hence, low power.
For Centaur, the WinChip 4 processor that founder Glenn Henry will describe is important in restoring parent IDT to profitability. WinChip3, with a 128-kbyte on-chip cache, began shipping earlier this year. But that microarchitecture, largely based on the core design of the original WinChip, was never designed to scale past 300 MHz, Henry said.
WinChip4 is a 400-to-500-MHz design set to debut in mid-1999 and be in volume production for next year's Christmas selling season.
"With WinChip4, we stuck with an in-order [execution] design. And we went with a very large L1 cache, 128 kbytes, with the fundamental belief that since it takes 30 to 50 clock cycles to recover from a cache miss, we wanted to do everything we could to make sure that doesn't happen," Henry said.
Centaur, with 50 employees and 22 design engineers, brings its own brand of sophistication to the X86 world. At the forum, Henry will describe a branch-targeting buffer and a branch-prediction capability that includes an agree/disagree function.
Tricks like those will keep the WinChip 4 die size small and the cost down, Centaur's primary objective.
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