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Politics : Formerly About Advanced Micro Devices
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To: Scumbria who wrote (39436)10/15/1998 9:21:00 PM
From: Tenchusatsu  Read Replies (1) of 1573862
 
Scumbria, re: <There are certain problems associated with building a 128K 2 way cache. The page size in windows is 4K and the implication of the large cache is that several bits of the cache index will have to come out of the TLB. This will require either 1) Several extra muxing stages at the data output to select from all the possible indexes, or 2) Holding off on the data access until the physical address is available from the TLB.>

I'm not sure I understand you fully. As I understand it, a 4-way L1 cache which is 16K+16K in size requires no tag bits from the TLB, because each "way" is 4K which is also the TLB page size, right? But a 2-way L1 cache which is 64K+64K in size will require three bits from the TLB, which could cause problems, right?

If that's so, and if Intel goes with a 32K+32K L1 cache in Katmai, how will they get around this problem?

Tenchusatsu
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